Catalog(6 parts)
| Part | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Input Capacitance▲▼ | Type | Supplier Device Package | Package / Case▲▼ | Package / Case | Mounting Type | Max Propagation Delay @ V, Max CL▲▼ | Trigger Type | Number of Bits per Element▲▼ | Number of Elements▲▼ | Output Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Current - Quiescent (Iq)▲▼ | Current - Output High, Low▲▼ | Clock Frequency▲▼ | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CY74FCT273CTSOCFlip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width) | 4.75 V | 5.25 V | 4.999999980020986e-12 F | D-Type | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | Surface Mount | 5.800000035804942e-9 s | Positive Edge | 8 ul | 1 ul | Non-Inverted | 85 °C | -40 °C | 0.00019999999494757503 A | 0.03200000151991844 A, 0.06400000303983688 A | |||||
4.75 V | 5.25 V | D-Type | 20-PDIP | 20-DIP | Through Hole | 7.000000135093387e-9 s | Positive Edge | 8 ul | 1 ul | Non-Inverted | 70 °C | 0 °C | 0.000007999999979801942 A | 70000000 Hz | 0.014999999664723871 A | 0.04800000041723251 A | 0.007619999814778566 m | 0.007619999814778566 m | ||||
Texas Instruments CY74FCT273ATSOCFlip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width) | 4.75 V | 5.25 V | 4.999999980020986e-12 F | D-Type | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | Surface Mount | 7.200000151641461e-9 s | Positive Edge | 8 ul | 1 ul | Non-Inverted | 85 °C | -40 °C | 0.00019999999494757503 A | 0.03200000151991844 A, 0.06400000303983688 A | |||||
Texas Instruments CY74FCT273CTSOCTE4Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width) | 4.75 V | 5.25 V | 4.999999980020986e-12 F | D-Type | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | Surface Mount | 5.800000035804942e-9 s | Positive Edge | 8 ul | 1 ul | Non-Inverted | 85 °C | -40 °C | 0.00019999999494757503 A | 0.03200000151991844 A, 0.06400000303983688 A | |||||
Texas Instruments CD74FCT273MFlip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width) | 4.75 V | 5.25 V | 9.999999960041972e-12 F | D-Type | 20-SOIC | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | Surface Mount | 7.000000135093387e-9 s | Positive Edge | 8 ul | 1 ul | Non-Inverted | 70 °C | 0 °C | 0.000007999999979801942 A | 70000000 Hz | 0.014999999664723871 A | 0.04800000041723251 A |
Key Features
• Function, Pinout, and Drive Compatible With FCT and F LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Fully Compatible With TTL Input and Output Logic LevelsCY54FCT273T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT273T64-mA Output Sink Current32-mA Output Source CurrentFunction, Pinout, and Drive Compatible With FCT and F LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Fully Compatible With TTL Input and Output Logic LevelsCY54FCT273T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT273T64-mA Output Sink Current32-mA Output Source Current
Description
AI
The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The \x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR\) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flop\x92s Q output. All outputs are forced low by a low logic level on the MR\ input.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.