TPS51206 Series

2A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference for DDR2/3/3L/4

Catalog(3 parts)

Part	Voltage - Input▲▼	Voltage - Input▲▼	Mounting Type	Operating Temperature▲▼	Operating Temperature▲▼	Voltage - Output▲▼	Voltage - Output▲▼	Supplier Device Package	Number of Outputs▲▼	Package / Case	Applications	Outputs and Type▲▼	Outputs and Type	Main Purpose	Current - Output▲▼	Supplied Contents	Board Type	Utilized IC / Part
Texas Instruments TPS51206DSQT - Converter, DDR Voltage Regulator IC 1 Output 10-WSON (2x2)	3.0999999046325684 V	6.5 V	Surface Mount	105 °C	-40 °C	0.8999999761581421 V	0.5 V	10-WSON (2x2)	1 ul	10-WFDFN Exposed Pad	Converter, DDR
Texas Instruments TPS51206DSQR - Converter, DDR Voltage Regulator IC 1 Output 10-WSON (2x2)	3.0999999046325684 V	6.5 V	Surface Mount	105 °C	-40 °C	0.8999999761581421 V	0.5 V	10-WSON (2x2)	1 ul	10-WFDFN Exposed Pad	Converter, DDR
Texas Instruments TPS51206EVM-745 TPS51206 - Special Purpose DC/DC, DDR Memory Supply 2, Non-Isolated Outputs Evaluation Board	3.0999999046325684 V	6.5 V										2 ul	Non-Isolated	DDR Memory Supply, Special Purpose DC/DC	0.009999999776482582 A, 2 A	Board(s)	Fully Populated	TPS51206

Key Features

• Supply Input Voltage: Supports 3.3-V Rail and 5-V RailVLDOIN Input Voltage Range: VTT+0.4 V to 3.5 VVTT Termination RegulatorOutput Voltage Range: 0.5 V to 0.9 V2-A Peak Sink and Source CurrentRequires Only 10-µF MLCC Output Capacitor±20 mV AccuracyVTTREF Buffered ReferenceVDDQ/2 ± 1% Accuracy10-mA Sink and Source CurrentSupports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 InputsOvertemperature Protection10-Pin, 2 mm × 2 mm SON (DSQ) PackageSupply Input Voltage: Supports 3.3-V Rail and 5-V RailVLDOIN Input Voltage Range: VTT+0.4 V to 3.5 VVTT Termination RegulatorOutput Voltage Range: 0.5 V to 0.9 V2-A Peak Sink and Source CurrentRequires Only 10-µF MLCC Output Capacitor±20 mV AccuracyVTTREF Buffered ReferenceVDDQ/2 ± 1% Accuracy10-mA Sink and Source CurrentSupports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 InputsOvertemperature Protection10-Pin, 2 mm × 2 mm SON (DSQ) Package

Description

The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk). The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C. The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk). The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.