74ALS112 Series

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

Catalog(3 parts)

Part	Type	Clock Frequency▲▼	Supplier Device Package	Current - Quiescent (Iq)▲▼	Trigger Type	Output Type	Package / Case	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Function	Max Propagation Delay @ V, Max CL▲▼	Number of Bits per Element▲▼	Number of Elements▲▼	Mounting Type	Operating Temperature▲▼	Package / Case▲▼
Texas Instruments SN74ALS112ANSR Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.209", 5.30mm Width)	JK Type	30000000 Hz	16-SO	0.0044999998062849045 A	Negative Edge	Complementary	16-SOIC (0.209", 5.30mm Width)	0.00800000037997961 A	0.00039999998989515007 A	5.5 V	4.5 V	Reset, Set(Preset)	1.8999999795710213e-8 s	1 ul	2 ul	Surface Mount	70 °C
Texas Instruments SN74ALS112ADR Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)	JK Type	30000000 Hz	16-SOIC	0.0044999998062849045 A	Negative Edge	Complementary	16-SOIC	0.00800000037997961 A	0.00039999998989515007 A	5.5 V	4.5 V	Reset, Set(Preset)	1.8999999795710213e-8 s	1 ul	2 ul	Surface Mount	70 °C	0.003911599982529879 m, 3.900000095367432 ul
Texas Instruments SN74ALS112AD Flip Flop 2 Element JK Type 1 Bit Negative Edge 16-SOIC (0.154", 3.90mm Width)	JK Type	30000000 Hz	16-SOIC	0.0044999998062849045 A	Negative Edge	Complementary	16-SOIC	0.00800000037997961 A	0.00039999998989515007 A	5.5 V	4.5 V	Reset, Set(Preset)	1.8999999795710213e-8 s	1 ul	2 ul	Surface Mount	70 °C	0.003911599982529879 m, 3.900000095367432 ul

Key Features

• Fully Buffered to Offer Maximum Isolation From External DisturbancePackage Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPsFully Buffered to Offer Maximum Isolation From External DisturbancePackage Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

Description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C. These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.