CD4522 Series

CMOS Programmable BCD Divide-By-N Counter

Catalog

CMOS Programmable BCD Divide-By-N Counter

Part	Mounting Type	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Package Name	Operating Temperature (Max)	Operating Temperature (Min)	Count Rate	Direction	Trigger Type	Reset	Logic Type	Package Width	Package Length	Number of Bits per Element	Number of Elements
Texas Instruments CD4522BMT	Surface Mount	3 V	18 V	16-SOIC	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	3.9 mm	0.154 in	4 bits	1
Texas Instruments CD4522BM	Surface Mount	3 V	18 V	16-SOIC	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	3.9 mm	0.154 in	4 bits	1
Texas Instruments CD4522BPWE4	Surface Mount	3 V	18 V	16-TSSOP	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	4.4 mm	0.173 in	4 bits	1
Texas Instruments CD4522BM96G4	Surface Mount	3 V	18 V	16-SOIC	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	3.9 mm	0.154 in	4 bits	1
Texas Instruments CD4522BNSR	Surface Mount	3 V	18 V	16-SO 16-SOIC	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	5.3 mm	0.209 in	4 bits	1
Texas Instruments CD4522BPW	Surface Mount	3 V	18 V	16-TSSOP	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	4.4 mm	0.173 in	4 bits	1
Texas Instruments CD4522BM96	Surface Mount	3 V	18 V	16-SOIC	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	3.9 mm	0.154 in	4 bits	1
Texas Instruments CD4522BE	Through Hole	3 V	18 V	16-DIP 16-PDIP	125 °C	-55 °C	8 MHz	Down	Negative Positive	Asynchronous	Divide-by-N	7.62 mm	0.3 in	4 bits	1

Catalog

CMOS Programmable BCD Divide-By-N Counter

Description

CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format. The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). CD4522B programmable BCD counter has a decoded "0" state output for divide-by-N applications. In single stage operation the "0" output is tied to the Preset Enable input. The Cascade Feedback allows multiple stage divide-by-N operation without the need for external gating. A HIGH on the Clock Inhibit disables the pulse-counting function. A HIGH on the Master Reset asynchronously resets the divide-by-N operation. The output is presented in BCD format. The CD4522B-series types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).