LMK04828 Series
Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
| Part | Function | Primary Attributes | Supplied Contents | Contents | Secondary Attributes | Type | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Number of Circuits | Voltage - Supply [Min] | Voltage - Supply [Max] | Package / Case | Mounting Type | PLL | Output | Divider/Multiplier | Frequency - Max [Max] | Input | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments LMK04828SNKDREP | |||||||||||||||||||||||
Texas Instruments LMK04828BEVM | Clock Conditioner | Jitter Cleaner | Board(s) | Board(s) | Integrated VCO | Timing | |||||||||||||||||
Texas Instruments LMK04828BISQX/NOPB | Jitter Cleaner | 3 | 15 | 1 | 3.15 V | 3.45 V | 64-WFQFN Exposed Pad | Surface Mount | HSDS, LCPECL, LVCMOS, LVDS, LVPECL | Yes/No | 3.08 GHz | LVCMOS, LVDS, LVPECL | -40 °C | 85 °C | 64-WQFN (9x9) | ||||||||
Texas Instruments LMK04828SNKDTEP | 64-WFQFN Exposed Pad | Surface Mount | 64-WQFN (9x9) | ||||||||||||||||||||
Texas Instruments LMK04828BISQ/NOPB | Jitter Cleaner | 3 | 15 | 1 | 3.15 V | 3.45 V | 64-WFQFN Exposed Pad | Surface Mount | HSDS, LCPECL, LVCMOS, LVDS, LVPECL | Yes/No | 3.08 GHz | LVCMOS, LVDS, LVPECL | -40 °C | 85 °C | 64-WQFN (9x9) | ||||||||
Texas Instruments LMK04828BISQE/NOPB | Jitter Cleaner | 3 | 15 | 1 | 3.15 V | 3.45 V | 64-WFQFN Exposed Pad | Surface Mount | HSDS, LCPECL, LVCMOS, LVDS, LVPECL | Yes/No | 3.08 GHz | LVCMOS, LVDS, LVPECL | -40 °C | 85 °C | 64-WQFN (9x9) |
Key Features
• JEDEC JESD204B SupportUltra-Low RMS Jitter88 fs RMS Jitter (12 kHz to 20 MHz)91 fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks from PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.1 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2Up to 1 Buffered VCXO/Crystal Output from PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switch-Over ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(even and odd)Precision Digital Delay, Dynamically Adjustable25-ps Step Analog DelayMulti-Mode: Dual PLL, Single PLL, and Clock DistributionIndustrial Temperature Range: –40 to 85°CSupports 105°C PCB Temperature (Measured at Thermal Pad)3.15-V to 3.45-V OperationPackage: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)JEDEC JESD204B SupportUltra-Low RMS Jitter88 fs RMS Jitter (12 kHz to 20 MHz)91 fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks from PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.1 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2Up to 1 Buffered VCXO/Crystal Output from PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switch-Over ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(even and odd)Precision Digital Delay, Dynamically Adjustable25-ps Step Analog DelayMulti-Mode: Dual PLL, Single PLL, and Clock DistributionIndustrial Temperature Range: –40 to 85°CSupports 105°C PCB Temperature (Measured at Thermal Pad)3.15-V to 3.45-V OperationPackage: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)
Description
AI
The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.
The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.
The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.