SN54HC138 Series

3-Line To 8-Line Decoders/Demultiplexers

Catalog

3-Line To 8-Line Decoders/Demultiplexers

Part	Package Width	Package Name	Package Length	Operating Temperature (Max)	Operating Temperature (Min)	Circuit	Independent Circuits	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Type	Voltage Supply Source	Mounting Type	Current - Output High	Current - Output Low	Package / Case
Texas Instruments M38510/65802BEA	7.62 mm	16-CDIP	0.3 in	125 °C	-55 °C	1 x 3:8	1	2 V	6 V	Decoder/Demultiplexer	Single Supply	Through Hole	5.2 mA	5.2 mA
Texas Instruments 8406201FA		16-CFP		125 °C	-55 °C	1 x 3:8	1	2 V	6 V	Decoder/Demultiplexer	Single Supply	Surface Mount	5.2 mA	5.2 mA	16-CFlatPack
Texas Instruments JM38510/65802B2A	8.89 mm	20-LCCC	8.89 mm	125 °C	-55 °C	1 x 3:8	1	2 V	6 V	Decoder/Demultiplexer	Single Supply	Surface Mount	5.2 mA	5.2 mA	20-CLCC
Texas Instruments SNJ54HC138J	7.62 mm	16-CDIP	0.3 in	125 °C	-55 °C	1 x 3:8	1	2 V	6 V	Decoder/Demultiplexer	Single Supply	Through Hole	5.2 mA	5.2 mA
Texas Instruments SNJ54HC138FK	8.89 mm	20-LCCC	8.89 mm	125 °C	-55 °C	1 x 3:8	1	2 V	6 V	Decoder/Demultiplexer	Single Supply	Surface Mount	5.2 mA	5.2 mA	20-CLCC
Texas Instruments 8406201EA	7.62 mm	16-CDIP	0.3 in	125 °C	-55 °C	1 x 3:8	1	2 V	6 V	Decoder/Demultiplexer	Single Supply	Through Hole	5.2 mA	5.2 mA

Catalog

3-Line To 8-Line Decoders/Demultiplexers

Description

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.