Catalog(1 parts)
| Part | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Number of Elements▲▼ | Number of Bits per Element▲▼ | Output Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Supplier Device Package | Mounting Type | Package / Case | Package / Case▲▼ | Current - Output High, Low▲▼ | Logic Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74ABT833NTTransceiver, Inverting 1 Element 8 Bit per Element Push-Pull Output 24-PDIP | 5.5 V | 4.5 V | 1 ul | 8 ul | Push-Pull | 85 °C | -40 °C | 24-PDIP | Through Hole | 24-DIP | 0.007619999814778566 m, 0.007619999814778566 m | 0.03200000151991844 A, 0.06400000303983688 A | Inverting, Transceiver |
Key Features
• State-of-the-Art EPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Parity Error Flag With Parity Generator/CheckerRegister for Storage of the Parity Error FlagPackage Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.State-of-the-Art EPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Parity Error Flag With Parity Generator/CheckerRegister for Storage of the Parity Error FlagPackage Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.
Description
AI
The 'ABT833 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error () output indicates whether or not an error in the B data has occurred. The output-enable (and) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT833 provide true data at their outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with theflag.is clocked into the register on the rising edge of the clock (CLK) input. The error flag register is cleared with a low pulse on the clear () input. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.
To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT833 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT833 is characterized for operation from -40°C to 85°C.
The 'ABT833 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error () output indicates whether or not an error in the B data has occurred. The output-enable (and) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT833 provide true data at their outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with theflag.is clocked into the register on the rising edge of the clock (CLK) input. The error flag register is cleared with a low pulse on the clear () input. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.
To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT833 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT833 is characterized for operation from -40°C to 85°C.