74ALVCH16374 Series

16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs

Catalog(8 parts)

Part	Operating Temperature▲▼	Operating Temperature▲▼	Type	Max Propagation Delay @ V, Max CL▲▼	Current - Output High, Low▲▼	Current - Output High, Low▲▼	Number of Bits per Element▲▼	Mounting Type	Package / Case	Input Capacitance▲▼	Clock Frequency▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Function	Number of Elements▲▼	Output Type	Trigger Type	Package / Case▲▼	Package / Case▲▼	Supplier Device Package	Max Propagation Delay @ V, Max CL▲▼
Texas Instruments SN74ALVCH16374DGVR Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.173", 4.40mm Width)	85 °C	-40 °C	D-Type	4.199999903420348e-9 s	0.024000000208616257 A	0.024000000208616257 A	8 ul	Surface Mount	48-TFSOP	2.9999999880125916e-12 F	150000000 Hz	3.5999999046325684 V	1.649999976158142 V	Standard	2 ul	Tri-State, Non-Inverted	Positive Edge
Texas Instruments 74ALVCH16374DGGRE4 Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)	85 °C	-40 °C	D-Type	4.199999903420348e-9 s	0.024000000208616257 A	0.024000000208616257 A	8 ul	Surface Mount	48-TFSOP	2.9999999880125916e-12 F	150000000 Hz	3.5999999046325684 V	1.649999976158142 V	Standard	2 ul	Tri-State, Non-Inverted	Positive Edge	0.006099999882280827 m	0.006095999851822853 m	48-TSSOP
Texas Instruments 74ALVCH16374ZQLR-P Flip Flop Element Bit
Texas Instruments SN74ALVCH16374DL Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-BSSOP (0.295", 7.50mm Width)	85 °C	-40 °C	D-Type	4.199999903420348e-9 s	0.024000000208616257 A	0.024000000208616257 A	8 ul	Surface Mount	48-BSSOP (0.295", 7.50mm Width)	2.9999999880125916e-12 F	150000000 Hz	3.5999999046325684 V	1.649999976158142 V	Standard	2 ul	Tri-State, Non-Inverted	Positive Edge			48-SSOP
Texas Instruments SN74ALVCH16374DGG Flip Flop Element Bit
Texas Instruments SN74ALVCH16374DLR Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-BSSOP (0.295", 7.50mm Width)	85 °C	-40 °C	D-Type	4.199999903420348e-9 s	0.024000000208616257 A	0.024000000208616257 A	8 ul	Surface Mount	48-BSSOP (0.295", 7.50mm Width)	2.9999999880125916e-12 F	150000000 Hz	3.5999999046325684 V	1.649999976158142 V	Standard	2 ul	Tri-State, Non-Inverted	Positive Edge			48-SSOP
Texas Instruments SN74ALVCH16374KR Flip Flop 2 Element D-Type 8 Bit Positive Edge 56-VFBGA	85 °C	-40 °C	D-Type	4.199999903420348e-9 s	0.024000000208616257 A	0.024000000208616257 A	8 ul	Surface Mount	56-VFBGA	2.9999999880125916e-12 F	150000000 Hz	3.5999999046325684 V	1.649999976158142 V	Standard	2 ul	Tri-State, Non-Inverted	Positive Edge			56-BGA Microstar Junior (7x4.5)
Texas Instruments SN74ALVCH16374DGGR Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)	85 °C	-40 °C	D-Type		0.024000000208616257 A	0.024000000208616257 A	8 ul	Surface Mount	48-TFSOP	2.9999999880125916e-12 F	150000000 Hz	3.5999999046325684 V	1.649999976158142 V	Standard	2 ul	Tri-State, Non-Inverted	Positive Edge	0.006099999882280827 m	0.006095999851822853 m	48-TSSOP	4.199999903420348e-9 s

Key Features

• Member of the Texas Instruments Widebus™ FamilyOperates From 1.65 to 3.6 VMax tpdof 4.2 ns at 3.3 V±24-mA Output Drive at 3.3 VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyOperates From 1.65 to 3.6 VMax tpdof 4.2 ns at 3.3 V±24-mA Output Drive at 3.3 VBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.

Description

This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation. The SN74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE\ can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation. The SN74ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE\ can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.