74AUP1T32 Series
Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, 2-Input Positive-OR Gate
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Features | Logic Type | Number of Inputs▲▼ | Number of Circuits▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case | Input Logic Level - Low▲▼ | Input Logic Level - Low▲▼ | Current - Quiescent (Max)▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Mounting Type | Max Propagation Delay @ V, Max CL▲▼ | Supplier Device Package | Input Logic Level - High▲▼ | Input Logic Level - High▲▼ | Current - Output High, Low▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Schmitt Trigger | OR Gate | 2 ul | 1 ul | -40 °C | 85 °C | 5-TSSOP, SC-70-5, SOT-353 | 0.5 V | 0.3499999940395355 V | 4.999999987376214e-7 A | 3.5999999046325684 V | 2.299999952316284 V | Surface Mount | 4.399999919968422e-9 s | SC-70-5 | 1.100000023841858 V | 1.190000057220459 V | 0.004000000189989805 A, 0.004000000189989805 A |
Key Features
• Single-Supply Voltage TranslatorOutput Level Up to Supply VCCCMOS Level1.8 V to 3.3 V (at VCC= 3.3 V)2.5 V to 3.3 V (at VCC= 3.3 V)1.8 V to 2.5 V (at VCC= 2.5 V)3.3 V to 2.5 V (at VCC= 2.5 VSchmitt-Trigger Inputs Reject Input Noise and ProvideBetter Output Signal IntegrityIoffSupports Partial Power Down (VCC= 0 V)Very Low Static Power Consumption:0.1 µAVery Low Dynamic Power Consumption:0.9 µALatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIPb-Free Packages Available: SC-70 (DCK)2 × 2.1 × 0.65 mm (Height 1.1 mm)More Gate Options Available atwww.ti.com/littlelogicESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)Single-Supply Voltage TranslatorOutput Level Up to Supply VCCCMOS Level1.8 V to 3.3 V (at VCC= 3.3 V)2.5 V to 3.3 V (at VCC= 3.3 V)1.8 V to 2.5 V (at VCC= 2.5 V)3.3 V to 2.5 V (at VCC= 2.5 VSchmitt-Trigger Inputs Reject Input Noise and ProvideBetter Output Signal IntegrityIoffSupports Partial Power Down (VCC= 0 V)Very Low Static Power Consumption:0.1 µAVery Low Dynamic Power Consumption:0.9 µALatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIPb-Free Packages Available: SC-70 (DCK)2 × 2.1 × 0.65 mm (Height 1.1 mm)More Gate Options Available atwww.ti.com/littlelogicESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)
Description
AI
The SN74AUP1T32 performs the Boolean function Y = A + B or Y =A\ • B\with designation for logic-level translation applications with output referenced to supply VCC.
AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCCsupply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The wide VCCrange of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.
Schmitt-trigger inputs (VT= 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioffis a feature that allows for powered-down conditions (VCC= 0 V) and is important in portable and mobile applications. When VCC= 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.
The SN74AUP1T32 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
The SN74AUP1T32 performs the Boolean function Y = A + B or Y =A\ • B\with designation for logic-level translation applications with output referenced to supply VCC.
AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCCsupply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The wide VCCrange of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.
Schmitt-trigger inputs (VT= 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioffis a feature that allows for powered-down conditions (VCC= 0 V) and is important in portable and mobile applications. When VCC= 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.
The SN74AUP1T32 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.