74AUC125 Series

4-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

Catalog

4-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

Part	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Package Length	Package Name	Package Width	Logic Type	Number of Elements	Mounting Type	Current - Output High	Current - Output Low	Output Type	Package / Case	Number of Bits per Element	Operating Temperature (Max)	Operating Temperature (Min)
Texas Instruments SN74AUC125RGYRG4	0.8 V	2.7 V	3.5 mm	14-VQFN	3.5 mm	Buffer Non-Inverting	4	Surface Mount	9 mA	9 mA	3-State	14-VFQFN Exposed Pad	1 bits	85 °C	-40 °C
Texas Instruments SN74AUC125RGYR	0.8 V	2.7 V	3.5 mm	14-VQFN	3.5 mm	Buffer Non-Inverting	4	Surface Mount	9 mA	9 mA	3-State	14-VFQFN Exposed Pad	1 bits	85 °C	-40 °C

Catalog

4-ch, 0.8-V to 2.7-V high speed buffers with 3-state outputs

Description

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCCoperation, but is designed specifically for 1.6-V to 1.95-V VCCoperation. The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCCoperation, but is designed specifically for 1.6-V to 1.95-V VCCoperation. The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.