SN74AUC00 Series

4-ch, 2-input, 0.8-V to 2.7-V high speed NAND gates

Catalog

4-ch, 2-input, 0.8-V to 2.7-V high speed NAND gates

Part	Input Logic Level - High [custom]	Number of Circuits	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Supplier Device Package	Package / Case	Max Propagation Delay @ V, Max CL	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Inputs	Current - Quiescent (Max) [Max]	Logic Type	Input Logic Level - Low [Min]	Input Logic Level - Low [Max]
Texas Instruments SN74AUC00RGYRG4	1.7 V	4	2.7 V	0.8 V	Surface Mount	14-VQFN (3.5x3.5)	14-VFQFN Exposed Pad	2 ns	9 mA	9 mA	85 °C	-40 °C	2	10 µA	NAND Gate	0 V	0.7 V
Texas Instruments SN74AUC00RGYR	1.7 V	4	2.7 V	0.8 V	Surface Mount	14-VQFN (3.5x3.5)	14-VFQFN Exposed Pad	2 ns	9 mA	9 mA	85 °C	-40 °C	2	10 µA	NAND Gate	0 V	0.7 V

Catalog

4-ch, 2-input, 0.8-V to 2.7-V high speed NAND gates

Key Features

• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 2 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal OperationIoffSupports Partial-Power-Down Mode OperationSub-1-V OperableMax tpdof 2 ns at 1.8 VLow Power Consumption, 10-µA Max ICC±8-mA Output Drive at 1.8 VLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This quadruple 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. The SN74AUC00 devices perform the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This quadruple 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation. The SN74AUC00 devices perform the Boolean function Y =A • Bor Y =A+Bin positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.