SN74SSTUB32864 Series

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTUB32864 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins. In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK andCLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the SN74SSTUB32864 ensures that the outputs remain low, thus ensuring there will be no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied,RESETmust be held in the low state during power up. The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low, exceptQERR. The LVCMOSRESETand Cn inputs always must be held at a valid logic high or low level. The device also supports low-power active operation by monitoring both system chip select (DCSandCSR) inputs and gates the Qn outputs from changing states when bothDCSandCSRinputs are high. If either DCS or CSR input is low, the Qn outputs function normally. TheRESETinput has priority over theDCSandCSRcontrol and, when driven low, forces the Qn outputs low. If theDCScontrol functionality is not desired, theCSRinput can be hard-wired to ground, in which case the setup-time requirement forDCSis the same as for the other D data inputs. To control the low-power mode withDCSonly, theCSRinput should be pulled up to VCCthrough a pullup resistor. The two VREFpins (A3 and T3) are connected together internally by approximately 150. However, it isnecessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications. The SN74SSTUB32864 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins. In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK andCLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the SN74SSTUB32864 ensures that the outputs remain low, thus ensuring there will be no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied,RESETmust be held in the low state during power up. The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low, exceptQERR. The LVCMOSRESETand Cn inputs always must be held at a valid logic high or low level. The device also supports low-power active operation by monitoring both system chip select (DCSandCSR) inputs and gates the Qn outputs from changing states when bothDCSandCSRinputs are high. If either DCS or CSR input is low, the Qn outputs function normally. TheRESETinput has priority over theDCSandCSRcontrol and, when driven low, forces the Qn outputs low. If theDCScontrol functionality is not desired, theCSRinput can be hard-wired to ground, in which case the setup-time requirement forDCSis the same as for the other D data inputs. To control the low-power mode withDCSonly, theCSRinput should be pulled up to VCCthrough a pullup resistor. The two VREFpins (A3 and T3) are connected together internally by approximately 150. However, it isnecessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor.