CDCM9102 Series

Low noise two channel 100-MHz PCIe clock generator

Catalog

Low noise two channel 100-MHz PCIe clock generator

Part	Supplied Contents	Utilized IC / Part	Primary Attributes	Secondary Attributes	Type	Contents	Function	Embedded	Operating Temperature (Min)	Operating Temperature (Max)	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Package / Case	Package Width	Package Name	Package Length	Multiplier	Divider	PLL	Input Ratio	Output Ratio	Input	Mounting Type	Differential Output	Differential Input	Output	Number of Circuits	Frequency - Max
Texas Instruments CDCM9102EVM	Board(s)	CDCM9102	1 Input 2 Outputs	SMA Connectors	Timing	Board	Clock Generator	No
Texas Instruments CDCM9102RHBR					Clock Generator				-40 °C	85 °C	3.6 V	3 V	32-VFQFN Exposed Pad	5 mm	32-VQFN	5 mm	No	No	No	1	3	Crystal	Surface Mount	Yes	No	LVCMOS LVDS LVPECL	1	100 MHz
Texas Instruments CDCM9102RHBT					Clock Generator				-40 °C	85 °C	3.6 V	3 V	32-VFQFN Exposed Pad	5 mm	32-VQFN	5 mm	No	No	No	1	3	Crystal	Surface Mount	Yes	No	LVCMOS LVDS LVPECL	1	100 MHz

Catalog

Low noise two channel 100-MHz PCIe clock generator

Description

The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal. The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.