CD74AC534 Series
Octal D-Type Flip-Flops with 3-State Outputs
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Octal D-Type Flip-Flops with 3-State Outputs
| Part | Number of Bits per Element | Voltage - Supply [Min] | Voltage - Supply [Max] | Clock Frequency | Mounting Type | Number of Elements [custom] | Trigger Type | Output Type | Type | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Function | Current - Quiescent (Iq) | Operating Temperature [Min] | Operating Temperature [Max] | Input Capacitance | Max Propagation Delay @ V, Max CL | Package / Case | Package / Case | Supplier Device Package |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74AC534M96 | 8 | 1.5 V | 5.5 V | 125 MHz | Surface Mount | 1 | Positive Edge | Tri-State, Inverted | D-Type | 24 mA | 24 mA | Standard | 8 ÁA | -55 C | 125 °C | 10 pF | 11.3 ns | 0.295 in, 7.5 mm | 20-SOIC | 20-SOIC |
Key Features
• SCR-Latch-up-resistant CMOS process and circuit designSpeed of bipolar FAST*/AS/S with significantly reduced power consumptionBalanced propagation delaysAC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply± 24mA output drive currentFanout to 15 FAST* ICsDrives 50ohm transmission lines(1)FAST is a Registered Trademark of Fairchild Semiconductor Corp.SCR-Latch-up-resistant CMOS process and circuit designSpeed of bipolar FAST*/AS/S with significantly reduced power consumptionBalanced propagation delaysAC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply± 24mA output drive currentFanout to 15 FAST* ICsDrives 50ohm transmission lines(1)FAST is a Registered Trademark of Fairchild Semiconductor Corp.
Description
AI
The eight flip-flops of the ’AC374 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
The eight flip-flops of the ’AC374 devices are D-type edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.