74AUP2G79 Series

Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop

Catalog

Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop

Part	Current - Output Low	Current - Output High	Type	Package Name	Package Length	Package Width	Max Propagation Delay	Max CL	Number of Elements	Input Capacitance	Trigger Type	Function	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Package / Case	Output Type	Clock Frequency	Number of Bits per Element	Current - Quiescent (Iq)	Operating Temperature (Max)	Operating Temperature (Min)	Mounting Type
Texas Instruments SN74AUP2G79DQER	4 mA	4 mA	D-Type	8-X2SON	1.4 mm	1 mm	6.3 ns	30 pF	2	1.5 pF	Positive Edge	Standard	0.8 V	3.6 V	8-XFDFN	Non-Inverted	266 MHz	1 bits	500 nA	85 °C	-40 °C	Surface Mount
Texas Instruments SN74AUP2G79YFPR	4 mA	4 mA	D-Type	8-DSBGA			6.3 ns	30 pF	2	1.5 pF	Positive Edge	Standard	0.8 V	3.6 V	8-XFBGA DSBGA	Non-Inverted	266 MHz	1 bits	500 nA	85 °C	-40 °C	Surface Mount
Texas Instruments SN74AUP2G79RSER	4 mA	4 mA	D-Type	8-UQFN	1.5 mm	1.5 mm	6.3 ns	30 pF	2	1.5 pF	Positive Edge	Standard	0.8 V	3.6 V	8-UFQFN	Non-Inverted	266 MHz	1 bits	500 nA	85 °C	-40 °C	Surface Mount
Texas Instruments SN74AUP2G79DCUR	4 mA	4 mA	D-Type	8-VFSOP 8-VSSOP	0.091 in	2.3 mm	6.3 ns	30 pF	2	1.5 pF	Positive Edge	Standard	0.8 V	3.6 V		Non-Inverted	266 MHz	1 bits	500 nA	85 °C	-40 °C	Surface Mount

Catalog

Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop

Description

The AUP family is TI’s premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The AUP family is TI’s premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.