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74HCT73 Series

High speed CMOS logic dual negative-edge-triggered J-K flip-flops with reset

Manufacturer: Texas Instruments

Catalog(3 parts)

PartNumber of Bits per ElementCurrent - Output High, LowFunctionInput CapacitanceVoltage - SupplyVoltage - SupplyOperating TemperatureOperating TemperatureOutput TypeTypeCurrent - Quiescent (Iq)Number of ElementsClock FrequencyMax Propagation Delay @ V, Max CLMounting TypeTrigger TypePackage / CasePackage / CasePackage / Case
Texas Instruments
CD74HCT73M
Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)
1 ul
0.004000000189989805 A, 0.004000000189989805 A
Reset
9.999999960041972e-12 F
5.5 V
4.5 V
-55 °C
125 °C
Complementary
JK Type
0.000003999999989900971 A
2 ul
60000000 Hz
3.7999999591420426e-8 s
Surface Mount
Negative Edge
0.003899999894201755 m
0.003911599982529879 m
14-SOIC
Texas Instruments
CD74HCT73E
Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-DIP (0.300", 7.62mm)
1 ul
0.004000000189989805 A, 0.004000000189989805 A
Reset
9.999999960041972e-12 F
5.5 V
4.5 V
-55 °C
125 °C
Complementary
JK Type
0.000003999999989900971 A
2 ul
60000000 Hz
3.7999999591420426e-8 s
Through Hole
Negative Edge
0.007619999814778566 m
0.007619999814778566 m
14-DIP
Texas Instruments
CD74HCT73EG4
Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-DIP (0.300", 7.62mm)
1 ul
0.004000000189989805 A, 0.004000000189989805 A
Reset
9.999999960041972e-12 F
5.5 V
4.5 V
-55 °C
125 °C
Complementary
JK Type
0.000003999999989900971 A
2 ul
60000000 Hz
3.7999999591420426e-8 s
Through Hole
Negative Edge
0.007619999814778566 m
0.007619999814778566 m
14-DIP

Key Features

Hysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOHHysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOH