74LVC1G79 Series

Enhanced Product Single Positive-Edge-Triggered D-Type Flip-Flop

Catalog

Enhanced Product Single Positive-Edge-Triggered D-Type Flip-Flop

Part	Number of Elements	Number of Bits per Element	Current - Output High	Current - Output Low	Current - Quiescent (Iq)	Type	Input Capacitance	Function	Trigger Type	Clock Frequency	Operating Temperature (Max)	Operating Temperature (Min)	Package Name	Mounting Type	Output Type	Package / Case	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Max Propagation Delay	Max CL	Qualification	Grade	Package Width	Package Length
Texas Instruments SN74LVC1G79DCKR	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	125 °C	-40 °C	SC-70-5	Surface Mount	Non-Inverted	5-TSSOP SC-70-5 SOT-353	1.65 V	5.5 V	4.5 ns	50 pF
Texas Instruments SN74LVC1G79DBVT	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	125 °C	-40 °C	SOT-23-5	Surface Mount	Non-Inverted		1.65 V	5.5 V	4.5 ns	50 pF
Texas Instruments SN74LVC1G79QDCKTQ1	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	125 °C	-40 °C	SC-70-5	Surface Mount	Non-Inverted	5-TSSOP SC-70-5 SOT-353	1.65 V	5.5 V	5 ns	50 pF	AEC-Q100	Automotive
Texas Instruments SN74LVC1G79DBVR	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	125 °C	-40 °C	SOT-23-5	Surface Mount	Non-Inverted		1.65 V	5.5 V	4.5 ns	50 pF
Texas Instruments SN74LVC1G79WDCKREP	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	115 °C	-55 °C	SC-70-5	Surface Mount	Non-Inverted	5-TSSOP SC-70-5 SOT-353	1.65 V	5.5 V	4.5 ns	50 pF
Texas Instruments SN74LVC1G79DCKRE4	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	125 °C	-40 °C	SC-70-5	Surface Mount	Non-Inverted	5-TSSOP SC-70-5 SOT-353	1.65 V	5.5 V	4.5 ns	50 pF
Texas Instruments SN74LVC1G79YEPR	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	85 °C	-40 °C	5-DSBGA	Surface Mount	Non-Inverted	5-XFBGA DSBGA	1.65 V	5.5 V	4.5 ns	50 pF			0.9 mm	1.4 mm
Texas Instruments SN74LVC1G79DBVTG4	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	125 °C	-40 °C	SOT-23-5	Surface Mount	Non-Inverted		1.65 V	5.5 V	4.5 ns	50 pF
Texas Instruments SN74LVC1G79YZAR	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	85 °C	-40 °C	5-DSBGA	Surface Mount	Non-Inverted	5-XFBGA DSBGA	1.65 V	5.5 V	4.5 ns	50 pF			0.9 mm	1.4 mm
Texas Instruments SN74LVC1G79DCKRG4	1	1 bits	32 mA	32 mA	10 µA	D-Type	4 pF	Standard	Positive Edge	160 MHz	125 °C	-40 °C	SC-70-5	Surface Mount	Non-Inverted	5-TSSOP SC-70-5 SOT-353	1.65 V	5.5 V	4.5 ns	50 pF

Catalog

Enhanced Product Single Positive-Edge-Triggered D-Type Flip-Flop

Description

The SN74LVC1G79 device is a single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. The SN74LVC1G79 device is a single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.