LP5899-Q1 Series

The LP5899-Q1 SPI-compatible connectivity enables LP589x-Q1 device family to be controlled using a standard SPI controller. The device features an internal oscillator to generate the continuous clock required by the LP589x-Q1 device family. Jitter can be added to the continuous clock for EMI enhancement. The transmitted data is aligned to the continuous clock to maintain the timing requirements of the CCSI interface. LP5899-Q1 incorporates reporting of faults in both the LP589x-Q1 daisy chain and LP5899-Q1 internal. Data transmission of register and VSYNC commands to the LP589x-Q1 daisy chain is CRC protected by LP5899-Q1. In addition, the data line is guarded by LP5899-Q1 for stuck-at faults. The LP5899-Q1 SPI-compatible connectivity enables LP589x-Q1 device family to be controlled using a standard SPI controller. The device features an internal oscillator to generate the continuous clock required by the LP589x-Q1 device family. Jitter can be added to the continuous clock for EMI enhancement. The transmitted data is aligned to the continuous clock to maintain the timing requirements of the CCSI interface. LP5899-Q1 incorporates reporting of faults in both the LP589x-Q1 daisy chain and LP5899-Q1 internal. Data transmission of register and VSYNC commands to the LP589x-Q1 daisy chain is CRC protected by LP5899-Q1. In addition, the data line is guarded by LP5899-Q1 for stuck-at faults.