74HCT299 Series
High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State Outputs
Manufacturer: Texas Instruments
Catalog(4 parts)
| Part | Output Type | Package / Case▲▼ | Package / Case | Logic Type | Mounting Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Function | Supplier Device Package | Number of Bits per Element▲▼ | Number of Elements▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Tri-State | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | Shift Register | Surface Mount | 5.5 V | 4.5 V | Universal | 20-SOIC | 8 ul | 2 ul | -55 °C | 125 °C | |||
Tri-State | 20-DIP | Shift Register | Through Hole | 5.5 V | 4.5 V | Universal | 20-PDIP | 8 ul | 2 ul | -55 °C | 125 °C | 0.007619999814778566 m | 0.007619999814778566 m | ||
Tri-State | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | Shift Register | Surface Mount | 5.5 V | 4.5 V | Universal | 20-SOIC | 8 ul | 2 ul | -55 °C | 125 °C | |||
Tri-State | 0.007493000011891127 m, 0.007499999832361937 m | 20-SOIC | Shift Register | Surface Mount | 5.5 V | 4.5 V | Universal | 20-SOIC | 8 ul | 2 ul | -55 °C | 125 °C |
Key Features
• Buffered InputsFour Operating Modes: Shift Left, Shift Right, Load and StoreCan be Cascaded for N-Bit Word LengthsI/O0– I/O7Bus Drive Capability and Three-State for Bus Oriented ApplicationsTypical fMAX= 50MHz at VCC=5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs. . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris SemiconductorBuffered InputsFour Operating Modes: Shift Left, Shift Right, Load and StoreCan be Cascaded for N-Bit Word LengthsI/O0– I/O7Bus Drive Capability and Three-State for Bus Oriented ApplicationsTypical fMAX= 50MHz at VCC=5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs. . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris Semiconductor
Description
AI
The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0– I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition.
The Master Reset (MR)\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.
The three-state input/output I(/O) port has three modes of operation:
1. Both output enable (OE1\ and OE2\) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for par-allel data to be loaded into eight registers with one clock transition regardless of the status of OE1\ and OE2\.
3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input.
The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0– I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be one set-up time prior to the clock positive transition.
The Master Reset (MR)\ is an asynchronous active low input. When MR\ output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.
The three-state input/output I(/O) port has three modes of operation:
1. Both output enable (OE1\ and OE2\) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for par-allel data to be loaded into eight registers with one clock transition regardless of the status of OE1\ and OE2\.
3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input.