CD74HC195 Series

High Speed CMOS Logic 4-Bit Parallel Access Register

Link to Manufacturer Page: https://www.ti.com/

Catalog

High Speed CMOS Logic 4-Bit Parallel Access Register

Part	Supplier Device Package	Number of Bits per Element	Function	Logic Type	Number of Elements [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case [x]	Package / Case	Package / Case [x]	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Output Type	Package / Case
Texas Instruments CD74HC195PW	16-TSSOP	4	Universal	Register, Bidirectional	1	2 V	6 V	0.173 "	16-TSSOP	4.4 mm	-55 °C	125 °C	Surface Mount	Complementary
Texas Instruments CD74HC195M96	16-SOIC	4	Universal	Register, Bidirectional	1	2 V	6 V		16-SOIC		-55 °C	125 °C	Surface Mount	Complementary	0.154 in, 3.9 mm Width
Texas Instruments CD74HC195NSR	16-SO	4	Universal	Register, Bidirectional	1	2 V	6 V		16-SOIC (0.209", 5.30mm Width)		-55 °C	125 °C	Surface Mount	Complementary
Texas Instruments CD74HC195M	16-SOIC	4	Universal	Register, Bidirectional	1	2 V	6 V		16-SOIC		-55 °C	125 °C	Surface Mount	Complementary	0.154 in, 3.9 mm Width
Texas Instruments CD74HC195PWR	16-TSSOP	4	Universal	Register, Bidirectional	1	2 V	6 V	0.173 "	16-TSSOP	4.4 mm	-55 °C	125 °C	Surface Mount	Complementary
Texas Instruments CD74HC195E	16-PDIP	4	Universal	Register, Bidirectional	1	2 V	6 V		16-DIP		-55 °C	125 °C	Through Hole	Complementary	0.3 in, 7.62 mm

Key Features

• Asynchronous Master ResetJ, K\,(D) Inputs to First StageFully Synchronous Serial or Parallel Data TransferShift Right and Parallel Load CapabilityComplementary Output From Last StageBuffered InputsTypical fMAX= 50MHz at VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . . 10 LSTTL LoadsBus Driver Outputs . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30%of VCCat VCC= 5VData sheet acquired from Harris SemiconductorAsynchronous Master ResetJ, K\,(D) Inputs to First StageFully Synchronous Serial or Parallel Data TransferShift Right and Parallel Load CapabilityComplementary Output From Last StageBuffered InputsTypical fMAX= 50MHz at VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . . 10 LSTTL LoadsBus Driver Outputs . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30%of VCCat VCC= 5VData sheet acquired from Harris Semiconductor

Description

The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qnoutputs to the Dn-1 inputs and holding the PE\ input low. All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The two modes of operation, shift right (Q0-Q1) and parallel load, are controlled by the state of the Parallel Enable (PE)\ input. Serial data enters the first flip-flop (Q0) via the J and K\ inputs when the PE\ input is high, and is shifted one bit in the direction Q0-Q1-Q2-Q3following each Low to High clock transition. The J and K\ inputs provide the flexibility of the JK-type input for special applications and by tying the two pins together, the simple D-type input for general applications. The device appears as four common-clocked D flip-flops when the PE\ input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the respective Q0-Q3outputs. Shift left operation (Q3-Q2) can be achieved by tying the Qnoutputs to the Dn-1 inputs and holding the PE\ input low. All parallel and serial data transfers are synchronous, occurring after each Low to High clock transition. The ’HC195 series utilizes edge triggering; therefore, there is no restriction on the activity of the J, K\, Pn and PE\ inputs for logic operations, other than set-up and hold time requirements. A Low on the asynchronous Master Reset (MR)\ input sets all Q outputs Low, independent of any other input condition.