CD74HC221 Series

High Speed CMOS Logic Dual Monostable Multivibrators with Reset

Link to Manufacturer Page: https://www.ti.com/

Catalog

High Speed CMOS Logic Dual Monostable Multivibrators with Reset

Part	Operating Temperature [Min]	Operating Temperature [Max]	Propagation Delay	Package / Case	Package / Case	Logic Type	Mounting Type	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low	Independent Circuits	Package / Case [x]	Package / Case [x]
Texas Instruments CD74HC221E	-55 °C	125 °C	18 ns	0.3 in, 7.62 mm	16-DIP	Monostable	Through Hole	16-PDIP	6 V	2 V	5.2 mA, 5.2 mA	2
Texas Instruments CD74HC221NSR	-55 °C	125 °C	18 ns		16-SOIC (0.209", 5.30mm Width)	Monostable	Surface Mount	16-SO	6 V	2 V	5.2 mA, 5.2 mA	2
Texas Instruments CD74HC221MT	-55 °C	125 °C	18 ns	0.154 in, 3.9 mm Width	16-SOIC	Monostable	Surface Mount	16-SOIC	6 V	2 V	5.2 mA, 5.2 mA	2
Texas Instruments CD74HC221M96	-55 °C	125 °C	18 ns	0.154 in, 3.9 mm Width	16-SOIC	Monostable	Surface Mount	16-SOIC	6 V	2 V	5.2 mA, 5.2 mA	2
Texas Instruments CD74HC221PW	-55 °C	125 °C	18 ns		16-TSSOP	Monostable	Surface Mount	16-TSSOP	6 V	2 V	5.2 mA, 5.2 mA	2	0.173 "	4.4 mm
Texas Instruments CD74HC221M	-55 °C	125 °C	18 ns	0.154 in, 3.9 mm Width	16-SOIC	Monostable	Surface Mount	16-SOIC	6 V	2 V	5.2 mA, 5.2 mA	2

Key Features

• Overriding RESET Terminates Output PulseTriggering from the Leading or Trailing EdgeQ and Q\ Buffered OutputsSeparate ResetsWide Range of Output-Pulse WidthsSchmitt Trigger on B InputsFanout (Over Temperature Range)Standard Outputs . . . . 10 LSTTL LoadsBus Driver Outputs . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris SemiconductorOverriding RESET Terminates Output PulseTriggering from the Leading or Trailing EdgeQ and Q\ Buffered OutputsSeparate ResetsWide Range of Output-Pulse WidthsSchmitt Trigger on B InputsFanout (Over Temperature Range)Standard Outputs . . . . 10 LSTTL LoadsBus Driver Outputs . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHData sheet acquired from Harris Semiconductor

Description

The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.7 RXCXat VCC= 4.5V. The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.7 RXCXat VCC= 4.5V.