Catalog(2 parts)
| Part | Frequency - Max▲▼ | Type | PLL▲▼ | Input | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case | Package / Case▲▼ | Supplier Device Package | Divider/Multiplier▲▼ | Divider/Multiplier▲▼ | Differential - Input:Output▲▼ | Differential - Input:Output▲▼ | Ratio - Input:Output▲▼ | Ratio - Input:Output▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Number of Circuits▲▼ | Mounting Type | Output |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
38000000 Hz | Phase Lock Loop (PLL) | CMOS | -55 °C | 125 °C | 16-SOIC | 0.003911599982529879 m, 3.900000095367432 ul | 16-SOIC | 4 ul | 1 ul | 5.5 V | 4.5 V | 1 ul | Surface Mount | CMOS | ||||||
38000000 Hz | Phase Lock Loop (PLL) | CMOS | -55 °C | 125 °C | 16-DIP | 0.007619999814778566 m, 0.007619999814778566 m | 16-PDIP | 4 ul | 1 ul | 5.5 V | 4.5 V | 1 ul | Through Hole | CMOS |
Key Features
• Operating Frequency RangeUp to 18MHz (Typ) at VCC= 5VMinimum Center Frequency of 12MHz at VCC= 4.5VChoice of Three Phase ComparatorsEXCLUSIVE-OREdge-Triggered JK Flip-FlopEdge-Triggered RS Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionMinimal Frequency DriftOperating Power Supply Voltage RangeVCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6VDigital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6VFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHApplicationsFM Modulation and DemodulationFrequency Synthesis and MultiplicationFrequency DiscriminationTone DecodingData Synchronization and ConditioningVoltage-to-Frequency ConversionMotor-Speed ControlOperating Frequency RangeUp to 18MHz (Typ) at VCC= 5VMinimum Center Frequency of 12MHz at VCC= 4.5VChoice of Three Phase ComparatorsEXCLUSIVE-OREdge-Triggered JK Flip-FlopEdge-Triggered RS Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionMinimal Frequency DriftOperating Power Supply Voltage RangeVCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6VDigital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6VFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il≤ 1µA at VOL, VOHApplicationsFM Modulation and DemodulationFrequency Synthesis and MultiplicationFrequency DiscriminationTone DecodingData Synchronization and ConditioningVoltage-to-Frequency ConversionMotor-Speed Control
Description
AI
The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.
The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.
The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.