Catalog(6 parts)
| Part | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case▲▼ | Package / Case | Supplier Device Package | Number of Outputs▲▼ | Voltage - Input▲▼ | Voltage - Input▲▼ | Mounting Type | Applications | Package / Case▲▼ | Package / Case▲▼ | Board Type | Channels per IC▲▼ | Utilized IC / Part | Regulator Type | Current - Output▲▼ | Supplied Contents | Qualification | Grade |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
125 °C | -40 °C | 0.003899999894201755 m | 8-SOIC | 8-SOIC | 1 ul | 5.5 V | 2.200000047683716 V | Surface Mount | Converter, DDR | |||||||||||
125 °C | -40 °C | 8-PowerSOIC | 8-SO PowerPad | 1 ul | 5.5 V | 2.200000047683716 V | Surface Mount | Converter, DDR | 0.003899999894201755 m | 0.003911599982529879 m | ||||||||||
Texas Instruments LP2998EVALLP2998 1 - Single Channels per IC Positive Fixed Linear Voltage Regulator Evaluation Board | 5.5 V | 2.200000047683716 V | Fully Populated | 1 ul | LP2998 | Positive Fixed | 1.5 A | Board(s) | ||||||||||||
125 °C | -40 °C | 8-PowerSOIC | 8-SO PowerPad | 1 ul | 5.5 V | 2.200000047683716 V | Surface Mount | Converter, DDR | 0.003899999894201755 m | 0.003911599982529879 m | AEC-Q100 | Automotive | ||||||||
125 °C | -40 °C | 0.003899999894201755 m | 8-SOIC | 8-SOIC | 1 ul | 5.5 V | 2.200000047683716 V | Surface Mount | Converter, DDR | |||||||||||
125 °C | -40 °C | 8-PowerSOIC | 8-SO PowerPad | 1 ul | 5.5 V | 2.200000047683716 V | Surface Mount | Converter, DDR | 0.003899999894201755 m | 0.003911599982529879 m |
Key Features
• AEC-Q100 Test Guidance with the following results(SO PowerPAD-8):Device HBM ESD Classification Level H1CJunction Temperature Range –40°C to 125°C1.35 V Minimum VDDQSource and Sink CurrentLow Output Voltage OffsetNo External Resistors RequiredLinear TopologySuspend to Ram (STR) FunctionalityLow External Component CountThermal ShutdownAEC-Q100 Test Guidance with the following results(SO PowerPAD-8):Device HBM ESD Classification Level H1CJunction Temperature Range –40°C to 125°C1.35 V Minimum VDDQSource and Sink CurrentLow Output Voltage OffsetNo External Resistors RequiredLinear TopologySuspend to Ram (STR) FunctionalityLow External Component CountThermal Shutdown
Description
AI
The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQmin of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREFoutput as a reference for the chipset and DIMMs.
An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. WhenSDis pulled low the VTToutput will tri-state providing a high impedance output, but, VREFwill remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQmin of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREFoutput as a reference for the chipset and DIMMs.
An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. WhenSDis pulled low the VTToutput will tri-state providing a high impedance output, but, VREFwill remain active. A power savings advantage can be obtained in this mode through lower quiescent current.