CDCLVD2106 Series

Low jitter, dual 1:6 universal-to-LVDS buffer

Link to Manufacturer Page: https://www.ti.com/

Catalog

Low jitter, dual 1:6 universal-to-LVDS buffer

Part	Package / Case	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Frequency - Max [Max]	Input	Number of Circuits	Mounting Type	Output	Type	Operating Temperature [Min]	Operating Temperature [Max]	Utilized IC / Part	Supplied Contents	Function	Primary Attributes
Texas Instruments CDCLVD2106RHAT	40-VFQFN Exposed Pad	6	1	2.375 V	2.625 V	40-VQFN (6x6)	800 MHz	LVCMOS, LVDS, LVPECL	2	Surface Mount	LVDS	Fanout Buffer (Distribution)	-40 °C	85 °C
Texas Instruments CDCLVD2106RHAR	40-VFQFN Exposed Pad	6	1	2.375 V	2.625 V	40-VQFN (6x6)	800 MHz	LVCMOS, LVDS, LVPECL	2	Surface Mount	LVDS	Fanout Buffer (Distribution)	-40 °C	85 °C
Texas Instruments CDCLVD2106EVM												Timing			CDCLVD2106	Board(s)	Clock Buffer	4 Ports, 12 Outputs

Key Features

• Dual 1:6 Differential BufferLow Additive Jitter: <300 fs rmsin 10 kHz – 20 MHzLow Within Bank Output Skew of 45 ps (Max)Universal Inputs Accept LVDS, LVPECL, LVCMOSOne Input Dedicated for Six OutputsTotal of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency up to 800 MHz2.375–2.625 V Device Power SupplyLVDS Reference Voltage, VAC_REF,Available for Capacitive Coupled InputsIndustrial Temperature Range –40°C to 85°CPackaged in 6 mm × 6 mm 40-pin QFN (RHA)ESD Protection Exceeds 3-kV HBM, 1-kV CDMAPPLICATIONSTelecommunications/NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose ClockingDual 1:6 Differential BufferLow Additive Jitter: <300 fs rmsin 10 kHz – 20 MHzLow Within Bank Output Skew of 45 ps (Max)Universal Inputs Accept LVDS, LVPECL, LVCMOSOne Input Dedicated for Six OutputsTotal of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency up to 800 MHz2.375–2.625 V Device Power SupplyLVDS Reference Voltage, VAC_REF,Available for Capacitive Coupled InputsIndustrial Temperature Range –40°C to 85°CPackaged in 6 mm × 6 mm 40-pin QFN (RHA)ESD Protection Exceeds 3-kV HBM, 1-kV CDMAPPLICATIONSTelecommunications/NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose Clocking

Description

The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal. The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package. The CDCLVD2106 clock buffer distributes two clock inputs (IN0, IN1) to a total of 12 pairs of differential LVDS clock outputs (OUT0, OUT11). Each buffer block consists of one input and 6 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD2106 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with six outputs is disabled and another buffer with six outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal. The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2106 is packaged in small 40-pin, 6-mm × 6-mm QFN package.