CD74AC00 Series

4-ch, 2-input, 1.5-V to 5.5-V NAND gates

Link to Manufacturer Page: https://www.ti.com/

Catalog

4-ch, 2-input, 1.5-V to 5.5-V NAND gates

Part	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Current - Quiescent (Max) [Max]	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Package / Case	Package / Case	Package / Case	Logic Type	Operating Temperature [Min]	Operating Temperature [Max]	Number of Inputs	Number of Circuits	Max Propagation Delay @ V, Max CL
Texas Instruments CD74AC00E	Through Hole	24 mA	24 mA	1.5 V	5.5 V	1.65 V	0.3 V	4 µA	3.85 V	1.2 V	14-DIP	7.62 mm	0.3 in	NAND Gate	-55 °C	125 °C	2	4	7.3 ns
Texas Instruments CD74AC00M	Surface Mount	24 mA	24 mA	1.5 V	5.5 V	1.65 V	0.3 V	4 µA	3.85 V	1.2 V	14-SOIC	3.9 mm	0.154 in	NAND Gate	-55 °C	125 °C	2	4	7.3 ns
Texas Instruments CD74AC00M96	Surface Mount	24 mA	24 mA	1.5 V	5.5 V	1.65 V	0.3 V	4 µA	3.85 V	1.2 V	14-SOIC	3.9 mm	0.154 in	NAND Gate	-55 °C	125 °C	2	4	7.3 ns

Key Features

• AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltageSpeed of bipolar F, AS, and S, with significantly reduced power consumptionBalanced propagation delays±24mA output drive current– Fanout to 15 F devicesSCR-latchup-resistant CMOS process and circuit designExceeds 2kV ESD protection per MIL-STD-883, method 3015AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltageSpeed of bipolar F, AS, and S, with significantly reduced power consumptionBalanced propagation delays±24mA output drive current– Fanout to 15 F devicesSCR-latchup-resistant CMOS process and circuit designExceeds 2kV ESD protection per MIL-STD-883, method 3015

Description

The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic. The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic.