CDCE6214 Series
Ultra-low power clock generator with one PLL, four differential output
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Ultra-low power clock generator with one PLL, four differential output
| Part | Qualification | Mounting Type | Divider/Multiplier | Grade | Output | Number of Circuits | Package / Case | Operating Temperature [Max] | Operating Temperature [Min] | Voltage - Supply [Max] | Voltage - Supply [Min] | PLL | Frequency - Max [Max] | Type | Input | Supplier Device Package | Function | Utilized IC / Part | Secondary Attributes | Supplied Contents | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCE6214TWRGETQ1 | AEC-Q100 | Surface Mount, Wettable Flank | Yes/No | Automotive | HCSL, LVCMOS, LVDS | 1 | 24-VFQFN Exposed Pad | 105 °C | -40 °C | 3.465 V | 1.71 V | 350 MHz | Clock Generator | Differential or Single-Ended | 24-VQFN (4x4) | |||||||||
Texas Instruments CDCE6214TWRGERQ1 | AEC-Q100 | Surface Mount, Wettable Flank | Yes/No | Automotive | HCSL, LVCMOS, LVDS | 1 | 24-VFQFN Exposed Pad | 105 °C | -40 °C | 3.465 V | 1.71 V | 350 MHz | Clock Generator | Differential or Single-Ended | 24-VQFN (4x4) | |||||||||
Texas Instruments CDCE6214-Q1EVM | Timing | Clock Generator | DCE6214-Q1 | USB Interface(s) | Board(s) | |||||||||||||||||||
Texas Instruments CDCE6214RGER | Surface Mount | Yes/No | LP-HCSL, LVCMOS, LVDS | 1 | 24-VFQFN Exposed Pad | 105 °C | -40 °C | 3.465 V | 1.71 V | 328.125 MHz | Clock Generator | Differential or Single-Ended, LVCMOS | 24-VQFN (4x4) | 2 | 5 | |||||||||
Texas Instruments CDCE6214RGET | Surface Mount, Wettable Flank | Yes/No | LP-HCSL, LVCMOS, LVDS | 1 | 24-VFQFN Exposed Pad | 85 °C | -40 °C | 3.465 V | 1.71 V | 350 MHz | Clock Generator | Differential or Single-Ended | 24-VQFN (4x4) | 2 | 4 |
Key Features
• Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout> 100 MHz) as:Integer mode:Differential output: 350 fs typical, 600 fs maximumLVCMOS output: 1.05 ps typical, 1.5 ps maximumFractional mode:Differential output: 1.7 ps typical, 2.1 ps maximumLVCMOS output: 2.0 ps typical, 4.0 ps maximumSupports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC2.335-GHz to 2.625-GHz internal VCOTypical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.Universal clock input, two reference inputs for redundancyDifferential AC-coupled or LVCMOS: 10 MHz to 200 MHzCrystal: 10 MHz to 50 MHzFlexible output clock distribution4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHzCombination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pinsGlitchless output divider switching and output channel synchronizationIndividual output enable through GPIO and registerFrequency margining optionsDCO mode: frequency increment/decrement with 10ppb or less step-sizeFully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHzSingle or mixed supply for level translation: 1.8 V/2.5 V/3.3 VConfigurable GPIOs and flexible configuration optionsI2C-compatible interface: up to 400 kHzIntegrated EEPROM with two pages and external select pin. In-situ programming allowed.Supports 100-Ω systemsLow electromagnetic emissionsSmall footprint: 24-pin VQFN (4 mm × 4 mm)Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, Fout> 100 MHz) as:Integer mode:Differential output: 350 fs typical, 600 fs maximumLVCMOS output: 1.05 ps typical, 1.5 ps maximumFractional mode:Differential output: 1.7 ps typical, 2.1 ps maximumLVCMOS output: 2.0 ps typical, 4.0 ps maximumSupports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC2.335-GHz to 2.625-GHz internal VCOTypical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.Universal clock input, two reference inputs for redundancyDifferential AC-coupled or LVCMOS: 10 MHz to 200 MHzCrystal: 10 MHz to 50 MHzFlexible output clock distribution4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHzCombination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pinsGlitchless output divider switching and output channel synchronizationIndividual output enable through GPIO and registerFrequency margining optionsDCO mode: frequency increment/decrement with 10ppb or less step-sizeFully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHzSingle or mixed supply for level translation: 1.8 V/2.5 V/3.3 VConfigurable GPIOs and flexible configuration optionsI2C-compatible interface: up to 400 kHzIntegrated EEPROM with two pages and external select pin. In-situ programming allowed.Supports 100-Ω systemsLow electromagnetic emissionsSmall footprint: 24-pin VQFN (4 mm × 4 mm)
Description
AI
The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.
On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.
Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.
The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.
The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I2C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.
On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.
Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.
The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.