Catalog(4 parts)
| Part | Output Type | Number of Elements▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Supplier Device Package | Operating Temperature▲▼ | Operating Temperature▲▼ | Mounting Type | Number of Bits per Element▲▼ | Current - Output High, Low▲▼ | Package / Case▲▼ | Package / Case▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74ABT543ADBTransceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-SSOP | 3-State | 1 ul | 5.5 V | 4.5 V | 0.005308600142598152 m | 0.0052999998442828655 m | 24-SSOP | 24-SSOP | 85 °C | -40 °C | Surface Mount | 8 ul | 0.03200000151991844 A, 0.06400000303983688 A | ||||
Texas Instruments SN74ABT543APWRTransceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-TSSOP | 3-State | 1 ul | 5.5 V | 4.5 V | 24-TSSOP | 24-TSSOP | 85 °C | -40 °C | Surface Mount | 8 ul | 0.03200000151991844 A, 0.06400000303983688 A | 0.004399999976158142 m | 0.004394200164824724 m | ||||
Texas Instruments SN74ABT543ADWRTransceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-SOIC | 3-State | 1 ul | 5.5 V | 4.5 V | 24-SOIC | 24-SOIC | 85 °C | -40 °C | Surface Mount | 8 ul | 0.03200000151991844 A, 0.06400000303983688 A | 0.007499999832361937 m | 0.007493000011891127 m | ||||
Texas Instruments SN74ABT543ADBRG4Transceiver, Non-Inverting 1 Element 8 Bit per Element 3-State Output 24-SSOP | 3-State | 1 ul | 5.5 V | 4.5 V | 0.005308600142598152 m | 0.0052999998442828655 m | 24-SSOP | 24-SSOP | 85 °C | -40 °C | Surface Mount | 8 ul | 0.03200000151991844 A, 0.06400000303983688 A |
Key Features
• State-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.State-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPsEPIC-IIB is a trademark of Texas Instruments Incorporated.
Description
AI
The 'ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA\, LEBA\, and OEBA\ inputs.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT543A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT543A is characterized for operation from -40°C to 85°C.
The 'ABT543A octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA\, LEBA\, and OEBA\ inputs.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT543A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT543A is characterized for operation from -40°C to 85°C.