74AS175 Series
Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Max Propagation Delay @ V, Max CL▲▼ | Number of Bits per Element▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Output Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Number of Elements▲▼ | Supplier Device Package | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Trigger Type | Clock Frequency▲▼ | Current - Quiescent (Iq)▲▼ | Mounting Type | Package / Case | Package / Case▲▼ | Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74AS175BDFlip Flop 1 Element D-Type 4 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width) | 9.99999993922529e-9 s | 4 ul | 5.5 V | 4.5 V | Complementary | 70 °C | 0 °C | 1 ul | 16-SOIC | 0.019999999552965164 A | 0.0020000000949949026 A | Positive Edge | 100000000 Hz | 0.03400000184774399 A | Surface Mount | 16-SOIC | 0.003911599982529879 m, 3.900000095367432 ul | D-Type |
Key Features
• ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)
Description
AI
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.