74FCT827 Series

10-ch, 4.75-V to 5.25-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Catalog(5 parts)

Part	Number of Elements▲▼	Mounting Type	Current - Output High, Low▲▼	Package / Case▲▼	Package / Case▲▼	Package / Case	Operating Temperature▲▼	Operating Temperature▲▼	Number of Bits per Element▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Supplier Device Package	Logic Type	Output Type
Texas Instruments CY74FCT827ATSOC Buffer, Non-Inverting 1 Element 10 Bit per Element 3-State Output 24-SOIC	1 ul	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A	0.007499999832361937 m	0.007493000011891127 m	24-SOIC	85 °C	-40 °C	10 ul	4.75 V	5.25 V	24-SOIC	Buffer, Non-Inverting	3-State
Texas Instruments CY74FCT827ATQCT Buffer, Non-Inverting 1 Element 10 Bit per Element 3-State Output 24-SSOP	1 ul	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A			24-SSOP	85 °C	-40 °C	10 ul	4.75 V	5.25 V	24-SSOP	Buffer, Non-Inverting	3-State
Texas Instruments CY74FCT827ATSOCT Buffer, Non-Inverting 1 Element 10 Bit per Element 3-State Output 24-SOIC	1 ul	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A	0.007499999832361937 m	0.007493000011891127 m	24-SOIC	85 °C	-40 °C	10 ul	4.75 V	5.25 V	24-SOIC	Buffer, Non-Inverting	3-State
Texas Instruments CY74FCT827CTSOC Buffer, Non-Inverting 1 Element 10 Bit per Element 3-State Output 24-SOIC	1 ul	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A	0.007499999832361937 m	0.007493000011891127 m	24-SOIC	85 °C	-40 °C	10 ul	4.75 V	5.25 V	24-SOIC	Buffer, Non-Inverting	3-State
Texas Instruments CY74FCT827CTQCTG4 Buffer, Non-Inverting 1 Element 10 Bit per Element 3-State Output 24-SSOP	1 ul	Surface Mount	0.03200000151991844 A, 0.06400000303983688 A			24-SSOP	85 °C	-40 °C	10 ul	4.75 V	5.25 V	24-SSOP	Buffer, Non-Inverting	3-State

Key Features

• Function, Pinout, and Drive Compatible With FCT, F, and AM29827 LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)3-State OutputsMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsCY54FCT827T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT827T64-mA Output Sink Current32-mA Output Source CurrentFunction, Pinout, and Drive Compatible With FCT, F, and AM29827 LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)3-State OutputsMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsCY54FCT827T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT827T64-mA Output Sink Current32-mA Output Source Current

Description

The \x92FCT827T devices are 10-bit bus drivers that provide high-performance bus-interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NANDed output enables for maximum control flexibility. The \x92FCT827T devices are designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT827T devices are 10-bit bus drivers that provide high-performance bus-interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NANDed output enables for maximum control flexibility. The \x92FCT827T devices are designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.