CD4012 Series

2-ch, 4-input, 3-V to 18-V NAND gates

Catalog

2-ch, 4-input, 3-V to 18-V NAND gates

Part	Max Propagation Delay	Max CL	Input Logic Level - High (Min)	Input Logic Level - High (Max)	Operating Temperature (Max)	Operating Temperature (Min)	Package Width	Package Name	Package Length	Number of Circuits	Input Logic Level - Low (Max)	Input Logic Level - Low (Min)	Mounting Type	Number of Inputs	Current - Quiescent (Max)	Current - Output Low	Current - Output High	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Logic Type
Texas Instruments CD4012BNS
Texas Instruments CD4012BMT	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	3.9 mm	14-SOIC	0.154 in	2	4 V	1.5 V	Surface Mount	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate
Texas Instruments CD4012BM96E4	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	3.9 mm	14-SOIC	0.154 in	2	4 V	1.5 V	Surface Mount	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate
Texas Instruments CD4012BEG4	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	7.62 mm	14-DIP 14-PDIP	0.3 in	2	4 V	1.5 V	Through Hole	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate
Texas Instruments CD4012BE	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	7.62 mm	14-DIP 14-PDIP	0.3 in	2	4 V	1.5 V	Through Hole	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate
Texas Instruments CD4012BM96	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	3.9 mm	14-SOIC	0.154 in	2	4 V	1.5 V	Surface Mount	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate
Texas Instruments CD4012BPWR	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	4.4 mm	14-TSSOP	0.173 in	2	4 V	1.5 V	Surface Mount	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate
Texas Instruments CD4012BM	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	3.9 mm	14-SOIC	0.154 in	2	4 V	1.5 V	Surface Mount	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate
Texas Instruments CD4012BNSR	90 ns	50 pF	3.5 V	11 V	125 °C	-55 °C	5.3 mm	14-SO 14-SOIC	0.209 in	2	4 V	1.5 V	Surface Mount	4	1 µA	3.4 mA	3.4 mA	3 V	18 V	NAND Gate

Catalog

2-ch, 4-input, 3-V to 18-V NAND gates

Description

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix). CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).