74AUP2G125 Series
2-ch, 0.8-V to 3.6-V low power buffers with 3-state outputs
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Logic Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Number of Bits per Element▲▼ | Number of Elements▲▼ | Supplier Device Package | Package / Case | Output Type | Mounting Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Current - Output High, Low▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74AUP2G125DQERBuffer, Non-Inverting 2 Element 1 Bit per Element 3-State Output 8-X2SON (1.4x1) | Buffer, Non-Inverting | 3.5999999046325684 V | 0.800000011920929 V | 1 ul | 2 ul | 8-X2SON (1.4x1) | 8-XFDFN | 3-State | Surface Mount | 85 °C | -40 °C | 0.004000000189989805 A, 0.004000000189989805 A |
Key Features
• Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Max)Low Dynamic-Power Consumption(Cpd= 4 pF Typ at 3.3 V)Low Input Capacitance (CI= 1.5 pF Typ)Low Noise – Overshoot and Undershoot<10% of VCCInput-Disable Feature Allows Floating Input ConditionsIoffSupports Partial-Power-Down Mode OperationInput Hysteresis Allows Slow Input Transition and Better SwitchingNoise Immunity at InputWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 5.4 ns Max at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)NanoStar is a trademark of Texas InstrumentsAvailable in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Max)Low Dynamic-Power Consumption(Cpd= 4 pF Typ at 3.3 V)Low Input Capacitance (CI= 1.5 pF Typ)Low Noise – Overshoot and Undershoot<10% of VCCInput-Disable Feature Allows Floating Input ConditionsIoffSupports Partial-Power-Down Mode OperationInput Hysteresis Allows Slow Input Transition and Better SwitchingNoise Immunity at InputWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 5.4 ns Max at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)NanoStar is a trademark of Texas Instruments
Description
AI
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCCoperation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCCoperation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.