Catalog(2 parts)
| Part | Mounting Type | Type | Data Rate (Max)▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Input | Current - Supply▲▼ | Package / Case▲▼ | Package / Case | Package / Case▲▼ | Delay Time▲▼ | Number of Channels | Number of Channels▲▼ | Supplier Device Package | Capacitance - Input▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Output |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Surface Mount | Buffer, Multiplexer | 419430400 bit/s | -40 °C | 85 °C | LVDS | 0.08500000089406967 A | 0.006095999851822853 m | 64-TFSOP | 0.006099999882280827 m | 2.800000009628434e-9 s | 2:16 | 1 ul | 64-TSSOP | 4.999999980020986e-12 F | 3.5999999046325684 V | 3 V | LVDS | |
Surface Mount | Buffer, Multiplexer | 419430400 bit/s | -40 °C | 85 °C | LVDS | 0.08500000089406967 A | 0.006095999851822853 m | 64-TFSOP | 0.006099999882280827 m | 2.800000009628434e-9 s | 2:16 | 1 ul | 64-TSSOP | 4.999999980020986e-12 F | 3.5999999046325684 V | 3 V | LVDS |
Key Features
• Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 StandardTypical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHzOutputs Arranged in Pairs From Each BankEnabling Logic Allows Individual Control of Each Driver Output Pair, Plus All OutputsLow-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω LoadElectrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination NetworksPropagation Delay Times < 4.5 nsOutput Skew Less Than 550 ps Bank Skew Less Than150 ps Part-to-Part Skew Less Than 1.5 nsTotal Power Dissipation Typically <500 mW With All Ports Enabled and at 200 MHzDriver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC< 1.5 VBus-Pin ESD Protection Exceeds 12 kVPackaged in Thin Shrink Small-Outline Package With 20-Mil Terminal PitchTwo Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 StandardTypical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHzOutputs Arranged in Pairs From Each BankEnabling Logic Allows Individual Control of Each Driver Output Pair, Plus All OutputsLow-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω LoadElectrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination NetworksPropagation Delay Times < 4.5 nsOutput Skew Less Than 550 ps Bank Skew Less Than150 ps Part-to-Part Skew Less Than 1.5 nsTotal Power Dissipation Typically <500 mW With All Ports Enabled and at 200 MHzDriver Outputs or Receiver Input Equals High Impedance When Disabled or With VCC< 1.5 VBus-Pin ESD Protection Exceeds 12 kVPackaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
Description
AI
The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four ('109) or eight ('117) differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of these devices, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock and data distribution trees.
The SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.
The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four ('109) or eight ('117) differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)
The intended application of these devices, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock and data distribution trees.
The SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.