TVP70025 Series

Triple 10-Bit 90-MSPS Video and Graphics Digitizer With Horizontal PLL

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Key Features

• Analog Channels–6-dB to 6-dB Analog GainAnalog Input Multiplexers (MUXs)Automatic Video ClampThree Digitizing Channels, Each With Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC)Clamping: Selectable Clamping Between Bottom Level and Mid LevelOffset: 1024-Step Programmable RGB or YPbPr Offset ControlGain: 8-Bit Programmable Gain ControlADC: 10-Bit 90-MSPS A/D ConverterAutomatic Level Control (ALC) CircuitComposite Sync: Integrated Sync-on-Green Extraction From Green/Luminance ChannelSupport for DC- and AC-Coupled Input SignalsProgrammable Video Bandwidth ControlSupports Component Video Standards 480i, 576i, 480p, 576p, 720p, and 1080iSupports PC Graphics Inputs up to 90 MSPSProgrammable RGB-to-YCbCr Color Space ConversionHorizontal Phase-Locked Loop (PLL)Fully Integrated Horizontal PLL for Pixel Clock Generation9-MHz to 90-MHz Pixel Clock Generation From HSYNC InputAdjustable Horizontal PLL Loop Bandwidth for Minimum Jitter5-Bit Programmable Subpixel Accurate Positioning of Sampling PhaseOutput FormatterSupports 20-bit 4:2:2 Outputs With Embedded SyncsSupport for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board TracesDedicated DATACLK Output With Programmable Output Polarity for Easy Latching of Output DataSystemIndustry-Standard Normal/Fast I2C Interface With Register Readback CapabilitySpace-Saving 100-Pin TQFP PackageThermally-Enhanced PowerPAD Package for Better Heat DissipationIndustrial Temperature Range –40°C to 85°CAnalog Channels–6-dB to 6-dB Analog GainAnalog Input Multiplexers (MUXs)Automatic Video ClampThree Digitizing Channels, Each With Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC)Clamping: Selectable Clamping Between Bottom Level and Mid LevelOffset: 1024-Step Programmable RGB or YPbPr Offset ControlGain: 8-Bit Programmable Gain ControlADC: 10-Bit 90-MSPS A/D ConverterAutomatic Level Control (ALC) CircuitComposite Sync: Integrated Sync-on-Green Extraction From Green/Luminance ChannelSupport for DC- and AC-Coupled Input SignalsProgrammable Video Bandwidth ControlSupports Component Video Standards 480i, 576i, 480p, 576p, 720p, and 1080iSupports PC Graphics Inputs up to 90 MSPSProgrammable RGB-to-YCbCr Color Space ConversionHorizontal Phase-Locked Loop (PLL)Fully Integrated Horizontal PLL for Pixel Clock Generation9-MHz to 90-MHz Pixel Clock Generation From HSYNC InputAdjustable Horizontal PLL Loop Bandwidth for Minimum Jitter5-Bit Programmable Subpixel Accurate Positioning of Sampling PhaseOutput FormatterSupports 20-bit 4:2:2 Outputs With Embedded SyncsSupport for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board TracesDedicated DATACLK Output With Programmable Output Polarity for Easy Latching of Output DataSystemIndustry-Standard Normal/Fast I2C Interface With Register Readback CapabilitySpace-Saving 100-Pin TQFP PackageThermally-Enhanced PowerPAD Package for Better Heat DissipationIndustrial Temperature Range –40°C to 85°C

Description

The TVP70025I is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 90 MHz. Therefore, it can be used for PC graphics digitizing up to WXGA (1440 × 900) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080i. The TVP70025I is powered from 3.3-V and 1.8-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP70025I includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP70025I can extract discrete HSYNC and VSYNC from composite sync using a sync slicer. The TVP70025I also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 9 MHz to 90 MHz. All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP70025I is available in a space-saving 100-pin TQFP PowerPAD package. The TVP70025I is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 90 MHz. Therefore, it can be used for PC graphics digitizing up to WXGA (1440 × 900) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080i. The TVP70025I is powered from 3.3-V and 1.8-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP70025I includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP70025I can extract discrete HSYNC and VSYNC from composite sync using a sync slicer. The TVP70025I also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 9 MHz to 90 MHz. All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP70025I is available in a space-saving 100-pin TQFP PowerPAD package.