CDCLVD1212 Series

Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer

Link to Manufacturer Page: https://www.ti.com/

Catalog

Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer

Part	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Input	Mounting Type	Output	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Frequency - Max [Max]	Package / Case	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Type	Number of Circuits
Texas Instruments CDCLVD1212RHAR	2	12	2.375 V	2.625 V	LVCMOS, LVDS, LVPECL	Surface Mount	LVDS	-40 °C	85 °C	40-VQFN (6x6)	800 MHz	40-VFQFN Exposed Pad			Fanout Buffer (Distribution), Multiplexer	1
Texas Instruments CDCLVD1212RHAT	2	12	2.375 V	2.625 V	LVCMOS, LVDS, LVPECL	Surface Mount	LVDS	-40 °C	85 °C	40-VQFN (6x6)	800 MHz	40-VFQFN Exposed Pad			Fanout Buffer (Distribution), Multiplexer	1

Key Features

• 2:12 Differential BufferLow Additive Jitter: < 300-fs RMS in10-kHz to 20-MHzLow Output Skew of 35 ps (Maximum)Universal Inputs Accept LVDS, LVPECL, and LVCMOSSelectable Clock Inputs Through Control Pin12 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency: Up to 800 MHzDevice Power Supply: 2.375 V to 2.625 VLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range: –40°C to 85°CPackaged in 6-mm × 6-mm, 40-Pin VQFN (RHA)ESD Protection Exceeds 3-kV HBM, 1-kV CDM2:12 Differential BufferLow Additive Jitter: < 300-fs RMS in10-kHz to 20-MHzLow Output Skew of 35 ps (Maximum)Universal Inputs Accept LVDS, LVPECL, and LVCMOSSelectable Clock Inputs Through Control Pin12 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency: Up to 800 MHzDevice Power Supply: 2.375 V to 2.625 VLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range: –40°C to 85°CPackaged in 6-mm × 6-mm, 40-Pin VQFN (RHA)ESD Protection Exceeds 3-kV HBM, 1-kV CDM

Description

The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11) with minimum skew for clock distribution. The CDCLVD1212 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD1212 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1212 is packaged in small, 40-pin, 6-mm × 6-mm VQFN package. The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11) with minimum skew for clock distribution. The CDCLVD1212 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS. The CDCLVD1212 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1212 is packaged in small, 40-pin, 6-mm × 6-mm VQFN package.