ADC12SJ1600 Series
Single-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Number of Bits▲▼ | Number of A/D Converters▲▼ | Configuration | Qualification | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Supplier Device Package | Operating Temperature▲▼ | Operating Temperature▲▼ | Data Interface | Mounting Type | Features | Grade | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Number of Inputs▲▼ | Reference Type | Sampling Rate (Per Second)▲▼ | Package / Case | Ratio - S/H:ADC | Architecture | Input Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC12SJ1600AAVTQ112 Bit Analog to Digital Converter 1 Input 4 Flash, Pipelined, SAR 144-FCBGA (10x10) | 12 ul | 4 ul | ADC | AEC-Q100 | 1.149999976158142 V, 2 V | 1.0499999523162842 V, 1.7999999523162842 V | 144-FCBGA (10x10) | 125 °C | -40 °C | JESD204C, SPI | Surface Mount | Temperature Sensor | Automotive | 1.149999976158142 V | 1.0499999523162842 V | 1 ul | External, Internal | 1600000000 Ω | 144-FBGA, FCBGA | 0:4 | Flash, Pipelined, SAR | Differential, Single Ended |
Key Features
• ADC Core:Resolution: 12 BitMaximum sampling rate: 1.6GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (100MHz): 57.4dBFSENOB (100MHz): 9.1 BitsSFDR (100MHz): 64dBcNoise floor (–20dBFS): –147dBFSFull-scale input voltage: 80mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad, Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2 to 8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1GSPS):Quad Channel: 477mW/channelDual channel: 700mW/channelSingle channel: 1000mWPower supplies: 1.1V, 1.9VADC Core:Resolution: 12 BitMaximum sampling rate: 1.6GSPSNon-interleaved architectureInternal dither reduces high-order harmonicsPerformance specifications (–1dBFS):SNR (100MHz): 57.4dBFSENOB (100MHz): 9.1 BitsSFDR (100MHz): 64dBcNoise floor (–20dBFS): –147dBFSFull-scale input voltage: 80mVPP-DIFFFull-power input bandwidth: 6GHzJESD204C Serial data interface:Support for 2 to 8 (Quad, Dual channel) or 1 to 4 (Single channel) total SerDes lanesMaximum baud-rate: 17.16Gbps64B/66B and 8B/10B encoding modesSubclass-1 support for deterministic latencyCompatible with JESD204B receiversOptional internal sampling clock generationInternal PLL and VCO (7.2 to 8.2GHz)SYSREF Windowing eases synchronizationFour clock outputs simplify system clockingReference clocks for FPGA or adjacent ADCReference clock for SerDes transceiversTimestamp input and output for pulsed systemsPower consumption (1GSPS):Quad Channel: 477mW/channelDual channel: 700mW/channelSingle channel: 1000mWPower supplies: 1.1V, 1.9V
Description
AI
ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems.
Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.