74ABT16501 Series
18-bit universal bus transceivers with 3-state outputs
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Current - Output High, Low▲▼ | Mounting Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Number of Circuits | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Package / Case | Package / Case▲▼ | Package / Case▲▼ | Supplier Device Package | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0.03200000151991844 A, 0.06400000303983688 A | Surface Mount | -40 °C | 85 °C | 18-Bit | 5.5 V | 4.5 V | 56-TFSOP | 0.006099999882280827 m | 0.006095999851822853 m | 56-TSSOP | |||
0.03200000151991844 A, 0.06400000303983688 A | Surface Mount | -40 °C | 85 °C | 18-Bit | 5.5 V | 4.5 V | 56-BSSOP | 56-SSOP | 0.007493000011891127 m | 0.007499999832361937 m |
Key Features
• Members of the Texas Instruments WidebusTMFamilyState-of-the-Art EPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationUBTTM(Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked ModeESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 5 V, TA= 25°CFlow-Through Architecture Optimizes PCB LayoutPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.Members of the Texas Instruments WidebusTMFamilyState-of-the-Art EPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationUBTTM(Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked ModeESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 5 V, TA= 25°CFlow-Through Architecture Optimizes PCB LayoutPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.
Description
AI
These 18-bit universal bus transceivers consist of storage elements that can operate either as D-type latches or D-type flip-flops to allow data flow in transparent or clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses, LEBA, and CLKBA. The output enables are complementary (OEAB is active high andis active low).
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor andshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sourcing/current-sinking capability of the driver.
The SN54ABT16501 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16501 is characterized for operation from -40°C to 85°C.
These 18-bit universal bus transceivers consist of storage elements that can operate either as D-type latches or D-type flip-flops to allow data flow in transparent or clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses, LEBA, and CLKBA. The output enables are complementary (OEAB is active high andis active low).
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor andshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sourcing/current-sinking capability of the driver.
The SN54ABT16501 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16501 is characterized for operation from -40°C to 85°C.