74AUP1G126 Series

Single 0.8-V to 3.6-V low power buffer with 3-state outputs

Catalog(7 parts)

Part	Number of Elements▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Number of Bits per Element▲▼	Package / Case	Logic Type	Output Type	Current - Output High, Low▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Supplier Device Package	Mounting Type	Supplier Device Package▲▼	Supplier Device Package▲▼
Texas Instruments 74AUP1G126DRLRG4 Buffer, Non-Inverting 1 Element 1 Bit per Element 3-State Output SOT-5	1 ul	85 °C	-40 °C	1 ul	SOT-553	Buffer, Non-Inverting	3-State	0.004000000189989805 A, 0.004000000189989805 A	3.5999999046325684 V	0.800000011920929 V	SOT-5	Surface Mount
Texas Instruments SN74AUP1G126DRYR Buffer, Non-Inverting 1 Element 1 Bit per Element 3-State Output 6-SON (1.45x1)	1 ul	85 °C	-40 °C	1 ul	6-UFDFN	Buffer, Non-Inverting	3-State	0.004000000189989805 A, 0.004000000189989805 A	3.5999999046325684 V	0.800000011920929 V	6-SON	Surface Mount	1 ul	1.4500000476837158 ul
Texas Instruments SN74AUP1G126YZPR Buffer, Non-Inverting 1 Element 1 Bit per Element 3-State Output 5-DSBGA (1.4x0.9)	1 ul	85 °C	-40 °C	1 ul	5-XFBGA, DSBGA	Buffer, Non-Inverting	3-State	0.004000000189989805 A, 0.004000000189989805 A	3.5999999046325684 V	0.800000011920929 V	5-DSBGA (1.4x0.9)	Surface Mount
Texas Instruments SN74AUP1G126DCKT Buffer, Non-Inverting 1 Element 1 Bit per Element 3-State Output SC-70-5	1 ul	85 °C	-40 °C	1 ul	5-TSSOP, SC-70-5, SOT-353	Buffer, Non-Inverting	3-State	0.004000000189989805 A, 0.004000000189989805 A	3.5999999046325684 V	0.800000011920929 V	SC-70-5	Surface Mount
Texas Instruments SN74AUP1G126DSFR Buffer, Non-Inverting 1 Element 1 Bit per Element 3-State Output 6-SON (1x1)	1 ul	85 °C	-40 °C	1 ul	6-XFDFN	Buffer, Non-Inverting	3-State	0.004000000189989805 A, 0.004000000189989805 A	3.5999999046325684 V	0.800000011920929 V	6-SON (1x1)	Surface Mount
Texas Instruments SN74AUP1G126DRLR Buffer, Non-Inverting 1 Element 1 Bit per Element 3-State Output SOT-5	1 ul	85 °C	-40 °C	1 ul	SOT-553	Buffer, Non-Inverting	3-State	0.004000000189989805 A, 0.004000000189989805 A	3.5999999046325684 V	0.800000011920929 V	SOT-5	Surface Mount
Texas Instruments SN74AUP1G126DBVT Buffer, Non-Inverting 1 Element 1 Bit per Element 3-State Output SOT-23-5	1 ul	85 °C	-40 °C	1 ul	SC-74A, SOT-753	Buffer, Non-Inverting	3-State	0.004000000189989805 A, 0.004000000189989805 A	3.5999999046325684 V	0.800000011920929 V	SOT-23-5	Surface Mount

Key Features

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 22−2000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Maximum)Low Dynamic-Power Consumption(Cpd= 4 pF Typical at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot<10% of VCCInput-Disable Feature Allows Floating Input ConditionsIoffSupports Partial-Power-Down Mode OperationInput Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at InputWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.6 ns Maximum at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 22−2000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Maximum)Low Dynamic-Power Consumption(Cpd= 4 pF Typical at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot<10% of VCCInput-Disable Feature Allows Floating Input ConditionsIoffSupports Partial-Power-Down Mode OperationInput Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at InputWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.6 ns Maximum at 3.3 VSuitable for Point-to-Point Applications

Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (seeAUP – The Lowest-Power FamilyandExcellent Signal Integrity). This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals. To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (seeAUP – The Lowest-Power FamilyandExcellent Signal Integrity). This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals. To assure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.