74AUP2G02 Series

2-ch, 2-input, 0.8-V to 3.6-V low power NOR gates

Catalog(3 parts)

Part	Number of Inputs▲▼	Package / Case	Current - Output High, Low▲▼	Input Logic Level - High▲▼	Input Logic Level - High▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Logic Type	Max Propagation Delay @ V, Max CL▲▼	Mounting Type	Supplier Device Package	Voltage - Supply▲▼	Voltage - Supply▲▼	Number of Circuits▲▼	Current - Quiescent (Max)▲▼
Texas Instruments SN74AUP2G02YFPR NOR Gate IC 2 Channel 8-DSBGA	2 ul	8-XFBGA, DSBGA	0.004000000189989805 A, 0.004000000189989805 A	1.600000023841858 V	2 V	-40 °C	85 °C	NOR Gate	6.20000006890109e-9 s	Surface Mount	8-DSBGA	3.5999999046325684 V	0.800000011920929 V	2 ul	4.999999987376214e-7 A
Texas Instruments SN74AUP2G02RSER NOR Gate IC 2 Channel 8-UQFN (1.5x1.5)	2 ul	8-UFQFN	0.004000000189989805 A, 0.004000000189989805 A	1.600000023841858 V	2 V	-40 °C	85 °C	NOR Gate	6.20000006890109e-9 s	Surface Mount	8-UQFN (1.5x1.5)	3.5999999046325684 V	0.800000011920929 V	2 ul	4.999999987376214e-7 A
Texas Instruments SN74AUP2G02DQER NOR Gate IC 2 Channel 8-X2SON (1.4x1)	2 ul	8-XFDFN	0.004000000189989805 A, 0.004000000189989805 A	1.600000023841858 V	2 V	-40 °C	85 °C	NOR Gate	6.20000006890109e-9 s	Surface Mount	8-X2SON (1.4x1)	3.5999999046325684 V	0.800000011920929 V	2 ul	4.999999987376214e-7 A

Key Features

• Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µ Maximum)Low Dynamic-Power Consumption(Cpd= 4.3 pF Typ at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot<10% of VCCIoffSupports Partial-Power-Down Mode OperationWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.3 ns Maximum at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)NanoStar is a trademark of Texas Instruments.Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µ Maximum)Low Dynamic-Power Consumption(Cpd= 4.3 pF Typ at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot<10% of VCCIoffSupports Partial-Power-Down Mode OperationWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.3 ns Maximum at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)NanoStar is a trademark of Texas Instruments.

Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2). The SN74AUP2G02 performs the Boolean function Y =A + Bor Y =A⋅Bin positive logic. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2). The SN74AUP2G02 performs the Boolean function Y =A + Bor Y =A⋅Bin positive logic. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.