ADC34J22 Series
Quad-Channel, 12-Bit, 50-MSPS Analog-to-Digital Converter (ADC)
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Quad-Channel, 12-Bit, 50-MSPS Analog-to-Digital Converter (ADC)
| Part | Package / Case | Data Interface | Reference Type | Operating Temperature [Min] | Operating Temperature [Max] | Voltage - Supply, Analog [Min] | Voltage - Supply, Analog [Max] | Number of Inputs | Number of A/D Converters | Voltage - Supply, Digital [Min] | Voltage - Supply, Digital [Max] | Input Type | Supplier Device Package | Number of Bits | Sampling Rate (Per Second) | Features | Architecture | Mounting Type | Configuration |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments ADC34J22IRGZT | 48-VFQFN Exposed Pad | JESD204B | External, Internal | -40 °C | 85 °C | 1.7 V | 1.9 V | 4 | 4 | 1.7 V | 1.9 V | Differential | 48-VQFN (7x7) | 12 | 50 M | Simultaneous Sampling | Pipelined | Surface Mount | ADC |
Texas Instruments ADC34J22IRGZR | 48-VFQFN Exposed Pad | JESD204B | External, Supply | -40 °C | 85 °C | 1.7 V | 1.9 V | 4 | 4 | 1.7 V | 1.9 V | Differential | 48-VQFN (7x7) | 12 | 50 M | Simultaneous Sampling | Pipelined | Surface Mount | ADC |
Key Features
• Quad Channel12-Bit ResolutionSingle 1.8-V SupplyFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 69.6 dBFS, SFDR = 86 dBc atfIN= 70 MHzUltra-Low Power Consumption:203 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Subclass 0, 1, 2 Compliant up to 3.2 GbpsSupports One Lane per ADC up to 160 MSPSSupport for Multi-Chip SynchronizationPin-to-Pin Compatible with 14-Bit VersionPackage: VQFN-48 (7 mm × 7 mm)Quad Channel12-Bit ResolutionSingle 1.8-V SupplyFlexible Input Clock Buffer with Divide-by-1, -2, -4SNR = 69.6 dBFS, SFDR = 86 dBc atfIN= 70 MHzUltra-Low Power Consumption:203 mW/Ch at 160 MSPSChannel Isolation: 105 dBInternal DitherJESD204B Serial Interface:Subclass 0, 1, 2 Compliant up to 3.2 GbpsSupports One Lane per ADC up to 160 MSPSSupport for Multi-Chip SynchronizationPin-to-Pin Compatible with 14-Bit VersionPackage: VQFN-48 (7 mm × 7 mm)
Description
AI
The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.
The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.