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74AVCH4T245 Series

4-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

Manufacturer: Texas Instruments

Catalog(9 parts)

PartMounting TypeNumber of Bits per Element▲▼Current - Output High, Low▲▼Current - Output High, Low▲▼Logic TypeNumber of Elements▲▼Voltage - Supply▲▼Voltage - Supply▲▼Output TypeSupplier Device PackagePackage / CasePackage / Case▲▼Operating Temperature▲▼Operating Temperature▲▼Supplier Device Package▲▼Supplier Device Package▲▼Package / Case▲▼Package / Case▲▼
Texas Instruments
SN74AVCH4T245D
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-SOIC
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
1.2000000476837158 V
3.5999999046325684 V
3-State
16-SOIC
16-SOIC
0.003911599982529879 m, 3.900000095367432 ul
85 °C
-40 °C
Texas Instruments
74AVCH4T245RSVR-NT
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-UQFN (2.6x1.8)
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
0.800000011920929 V
3.5999999046325684 V
3-State
16-UQFN
16-UFQFN
85 °C
-40 °C
1.7999999523162842 ul
2.5999999046325684 ul
Texas Instruments
SN74AVCH4T245RSVR
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-UQFN (2.6x1.8)
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
1.2000000476837158 V
3.5999999046325684 V
3-State
16-UQFN
16-UFQFN
85 °C
-40 °C
1.7999999523162842 ul
2.5999999046325684 ul
Texas Instruments
SN74AVCH4T245DGVR
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-TVSOP
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
1.2000000476837158 V
3.5999999046325684 V
3-State
16-TVSOP
16-TFSOP
0.004394200164824724 m, 0.004399999976158142 m
85 °C
-40 °C
Texas Instruments
SN74AVCH4T245DR
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-SOIC
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
1.2000000476837158 V
3.5999999046325684 V
3-State
16-SOIC
16-SOIC
0.003911599982529879 m, 3.900000095367432 ul
85 °C
-40 °C
Texas Instruments
SN74AVCH4T245PWE4
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-TSSOP
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
1.2000000476837158 V
3.5999999046325684 V
3-State
16-TSSOP
16-TSSOP
85 °C
-40 °C
0.004394200164824724 m
0.004399999976158142 m
Texas Instruments
SN74AVCH4T245PWR
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-TSSOP
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
1.2000000476837158 V
3.5999999046325684 V
3-State
16-TSSOP
16-TSSOP
85 °C
-40 °C
0.004394200164824724 m
0.004399999976158142 m
Texas Instruments
74AVCH4T245RSVRG4
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-UQFN (2.6x1.8)
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
0.800000011920929 V
3.5999999046325684 V
3-State
16-UQFN
16-UFQFN
85 °C
-40 °C
1.7999999523162842 ul
2.5999999046325684 ul
Texas Instruments
74AVCH4T245PWTE4
Translation Transceiver 2 Element 2 Bit per Element 3-State Output 16-TSSOP
Surface Mount
2 ul
0.012000000104308128 A
0.012000000104308128 A
Translation Transceiver
2 ul
0.800000011920929 V
3.5999999046325684 V
3-State
16-TSSOP
16-TSSOP
85 °C
-40 °C
0.004394200164824724 m
0.004399999976158142 m

Key Features

• Control inputs VIH/VIL levels are referenced to VCCA voltageFully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply rangeI/Os Are 4.6V TolerantIoff supports partial power-down-mode operationBus hold on data inputs eliminates the need for external pull-up/pull-down resistorsSupports data rate up to:380Mbps (1.8V to 3.3V Translation)200Mbps (<1.8V to 3.3V Translation)200Mbps (Translate to 2.5V or 1.8V)150Mbps (Translate to 1.5V)100Mbps (Translate to 1.2V)Latch-up performance exceeds 100mA per JESD 78, class IIESD protection exceeds JESD 22:8000V Human Body Model (A114-A)200V Machine Model (A115-A)1000V Charged-Device Model (C101)Control inputs VIH/VIL levels are referenced to VCCA voltageFully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply rangeI/Os Are 4.6V TolerantIoff supports partial power-down-mode operationBus hold on data inputs eliminates the need for external pull-up/pull-down resistorsSupports data rate up to:380Mbps (1.8V to 3.3V Translation)200Mbps (<1.8V to 3.3V Translation)200Mbps (Translate to 2.5V or 1.8V)150Mbps (Translate to 1.5V)100Mbps (Translate to 1.2V)Latch-up performance exceeds 100mA per JESD 78, class IIESD protection exceeds JESD 22:8000V Human Body Model (A114-A)200V Machine Model (A115-A)1000V Charged-Device Model (C101)

Description

AI
This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVCH4T245 is optimized to operate with VCCA/VCCB set at 1.2V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes. The SN74AVCH4T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74AVCH4T245 device control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry on the powered-up side always stays active. To put the device in the high-impedance state during power up or power down, tie the OE pin to VCC through a pull-up resistor; the current-sinking capability of the driver determines the minimum value of the resistor. This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVCH4T245 is optimized to operate with VCCA/VCCB set at 1.2V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes. The SN74AVCH4T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74AVCH4T245 device control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry on the powered-up side always stays active. To put the device in the high-impedance state during power up or power down, tie the OE pin to VCC through a pull-up resistor; the current-sinking capability of the driver determines the minimum value of the resistor.