UCC38084 Series

The UCC38083/4/5/6 is a family of BiCMOS pulse width modulation (PWM) controllers for dc-to-dc or off-line fixed-frequency current-mode switching power supplies. The dual output stages are configured for the push-pull topology. Both outputs switch at half the oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 110 ns, limiting each output’s duty cycle to less than 50%. The new UCC3808x family is based on the UCC3808A architecture. The major differences include the addition of a programmable slope compensation ramp to the CS signal and the removal of the error amplifier. The current flowing out of the ISET pin through an external resistor is monitored internally to set the magnitude of the slope compensation function. This device also includes an internal discharge transistor from the CS pin to ground, which is activated at each clock cycle after the pulse is terminated. This discharges any filter capacitance on the CS pin during each cycle and helps minimize filter capacitor values and current sense delay. The UCC38083 and the UCC38084 devices have a typical soft-start interval time of 3.5 ms while the UCC38085 and the UCC38086 has less than 100 µs for applications where internal soft-start is not desired. The UCC38083 and the UCC38085 devices have the turn on/off thresholds of the 12.5 V / 8.3 V, while the UCC38084 and the UCC38086 has the turn on/off thresholds of 4.3 V / 4.1 V. Each device is offered in 8-pin TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P) packages. The UCC38083/4/5/6 is a family of BiCMOS pulse width modulation (PWM) controllers for dc-to-dc or off-line fixed-frequency current-mode switching power supplies. The dual output stages are configured for the push-pull topology. Both outputs switch at half the oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 110 ns, limiting each output’s duty cycle to less than 50%. The new UCC3808x family is based on the UCC3808A architecture. The major differences include the addition of a programmable slope compensation ramp to the CS signal and the removal of the error amplifier. The current flowing out of the ISET pin through an external resistor is monitored internally to set the magnitude of the slope compensation function. This device also includes an internal discharge transistor from the CS pin to ground, which is activated at each clock cycle after the pulse is terminated. This discharges any filter capacitance on the CS pin during each cycle and helps minimize filter capacitor values and current sense delay. The UCC38083 and the UCC38084 devices have a typical soft-start interval time of 3.5 ms while the UCC38085 and the UCC38086 has less than 100 µs for applications where internal soft-start is not desired. The UCC38083 and the UCC38085 devices have the turn on/off thresholds of the 12.5 V / 8.3 V, while the UCC38084 and the UCC38086 has the turn on/off thresholds of 4.3 V / 4.1 V. Each device is offered in 8-pin TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P) packages.