74AUP2G80 Series

Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop

Catalog(2 parts)

Part	Max Propagation Delay @ V, Max CL▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Clock Frequency▲▼	Output Type▲▼	Mounting Type	Function	Operating Temperature▲▼	Operating Temperature▲▼	Type	Supplier Device Package	Current - Output High, Low▲▼	Trigger Type	Number of Elements▲▼	Package / Case	Input Capacitance▲▼	Number of Bits per Element▲▼
Texas Instruments SN74AUP2G80DQER Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFDFN	6.4000000854491645e-9 s	3.5999999046325684 V	0.800000011920929 V	257000000 Hz	27.030000686645508 °C/W	Surface Mount	Standard	85 °C	-40 °C	D-Type	8-X2SON (1.4x1)	0.004000000189989805 A, 0.004000000189989805 A	Positive Edge	2 ul	8-XFDFN	1.4999999940062958e-12 F	1 ul
Texas Instruments SN74AUP2G80YFPR Flip Flop 2 Element D-Type 1 Bit Positive Edge 8-XFBGA, DSBGA	6.4000000854491645e-9 s	3.5999999046325684 V	0.800000011920929 V	257000000 Hz	27.030000686645508 °C/W	Surface Mount	Standard	85 °C	-40 °C	D-Type	8-DSBGA	0.004000000189989805 A, 0.004000000189989805 A	Positive Edge	2 ul	8-XFBGA, DSBGA	1.4999999940062958e-12 F	1 ul

Key Features

• Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Maximum)Low Dynamic-Power Consumption(Cpd= 4.3 pF Typ at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot<10% of VCCIoffSupports Partial-Power-Down Mode OperationWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.4 ns Maximum at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoStar™ PackageLow Static-Power Consumption(ICC= 0.9 µA Maximum)Low Dynamic-Power Consumption(Cpd= 4.3 pF Typ at 3.3 V)Low Input Capacitance (Ci= 1.5 pF Typical)Low Noise – Overshoot and Undershoot<10% of VCCIoffSupports Partial-Power-Down Mode OperationWide Operating VCCRange of 0.8 V to 3.6 VOptimized for 3.3-V Operation3.6-V I/O Tolerant to Support Mixed-Mode Signal Operationtpd= 4.4 ns Maximum at 3.3 VSuitable for Point-to-Point ApplicationsLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Performance Tested Per JESD 222000-V Human-Body Model(A114-B, Class II)1000-V Charged-Device Model (C101)

Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2). When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2). When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.