74LS156 Series

Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs

Catalog(3 parts)

Part	Operating Temperature▲▼	Mounting Type	Voltage - Supply▲▼	Voltage - Supply▲▼	Package / Case	Package / Case▲▼	Voltage Supply Source	Supplier Device Package	Current - Output High, Low▲▼	Circuit▲▼	Circuit	Independent Circuits▲▼	Type
Texas Instruments SN74LS156D Decoder/Demultiplexer 2 x 1:4 16-SOIC	70 °C	Surface Mount	4.75 V	5.25 V	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Single Supply	16-SOIC	0.00009999999747378752 A, 0.00800000037997961 A	2 ul	1:4	1 ul	Decoder/Demultiplexer
Texas Instruments SN74LS156N Decoder/Demultiplexer 2 x 1:4 16-PDIP	70 °C	Through Hole	4.75 V	5.25 V	16-DIP	0.007619999814778566 m, 0.007619999814778566 m	Single Supply	16-PDIP	0.00009999999747378752 A, 0.00800000037997961 A	2 ul	1:4	1 ul	Decoder/Demultiplexer
Texas Instruments SN74LS156DR Decoder/Demultiplexer 2 x 1:4 16-SOIC	70 °C	Surface Mount	4.75 V	5.25 V	16-SOIC	0.003911599982529879 m, 3.900000095367432 ul	Single Supply	16-SOIC	0.00009999999747378752 A, 0.00800000037997961 A	2 ul	1:4	1 ul	Decoder/Demultiplexer

Key Features

• Applications:Dual 2-to 4-Line DecoderDual 1-to 4-Line Demultiplexer3-to 8-Line Decoder1-to 8-Line DemultiplexerIndividual Strobes Simplify Cascading for Decoding or Demultiplexing Larger WordsInput Clamping Diodes Simplify System DesignChoice of Outputs:Totem Pole ('155, 'LS155A)Open-Collector ('156, 'LS156)Applications:Dual 2-to 4-Line DecoderDual 1-to 4-Line Demultiplexer3-to 8-Line Decoder1-to 8-Line DemultiplexerIndividual Strobes Simplify Cascading for Decoding or Demultiplexing Larger WordsInput Clamping Diodes Simplify System DesignChoice of Outputs:Totem Pole ('155, 'LS155A)Open-Collector ('156, 'LS156)

Description

These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design. These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.