AD3421 Series
Automotive quad-channel 12-bit 25-MSPS analog-to-digital converter (ADC)
Manufacturer: Texas Instruments
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Key Features
• AEC-Q100 Qualified for automotive applicationsTemperature grade 1: –40°C to 125°C TAQuad channel12-Bit resolutionSingle supply: 1.8 VSerial LVDS interfaceFlexible input clock buffer with divide-by-1, -2, -4SNR = 71.1 dBFS, SFDR = 90 dBc atfIN= 10 MHzUltra-low power consumption:44 mW/Ch at 25 MSPSChannel isolation: 105 dBInternal dither and chopperSupport for multichip synchronizationAEC-Q100 Qualified for automotive applicationsTemperature grade 1: –40°C to 125°C TAQuad channel12-Bit resolutionSingle supply: 1.8 VSerial LVDS interfaceFlexible input clock buffer with divide-by-1, -2, -4SNR = 71.1 dBFS, SFDR = 90 dBc atfIN= 10 MHzUltra-low power consumption:44 mW/Ch at 25 MSPSChannel isolation: 105 dBInternal dither and chopperSupport for multichip synchronization
Description
AI
The ADC3421-Q1 is an automotive-grade, high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider gives more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization. The ADC3421-Q1 supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
The ADC3421-Q1 is an automotive-grade, high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider gives more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization. The ADC3421-Q1 supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.