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CDCL1810A Series

1.8-V 1-to-10 high performance differential clock buffer with individual output enable/disable

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

1.8-V 1-to-10 high performance differential clock buffer with individual output enable/disable

PartVoltage - Supply [Min]Voltage - Supply [Max]OutputSupplier Device PackageTypeRatio - Input:Output [custom]Ratio - Input:Output [custom]InputFrequency - Max [Max]Operating Temperature [Min]Operating Temperature [Max]Differential - Input:Output [custom]Differential - Input:Output [custom]Package / CaseMounting TypeNumber of Circuits
Texas Instruments
CDCL1810ARGZT
1.7 V
1.9 V
CML
48-VQFN (7x7)
Fanout Buffer (Distribution), Divider
1
10
LVDS
650 MHz
-40 °C
85 °C
48-VFQFN Exposed Pad
Surface Mount
1

Key Features

othersSingle 1.8 V SupplyHigh-Performance Clock Distributor with 10 OutputsLow Input-to-Output Additive Jitter: as low as 10fs RMSLow-Voltage Differential Signaling (LVDS) Input, 100ΩDifferential On-Chip Termination, up to 650 MHz FrequencyDifferential Current Mode Logic (CML) Outputs, 50ΩSingle-Ended On-Chip Termination, up to 650 MHz FrequencyTwo Groups of Five Outputs Each with Independent FrequencyDivision RatiosOutput Frequency Derived with Divide Ratios of 1, 2, 4, 5,8, 10, 16, 20, 32, 40, and 80Meets ANSI TIA/EIA-644-A-2001 LVDS Standard RequirementsPower Consumption: 410 mW TypicalOutput Enable Control for Each OutputSDA/SCL Device Management Interface48-pin VQFN (RGZ) PackageIndustrial Temperature Range: –40°C to +85°CothersSingle 1.8 V SupplyHigh-Performance Clock Distributor with 10 OutputsLow Input-to-Output Additive Jitter: as low as 10fs RMSLow-Voltage Differential Signaling (LVDS) Input, 100ΩDifferential On-Chip Termination, up to 650 MHz FrequencyDifferential Current Mode Logic (CML) Outputs, 50ΩSingle-Ended On-Chip Termination, up to 650 MHz FrequencyTwo Groups of Five Outputs Each with Independent FrequencyDivision RatiosOutput Frequency Derived with Divide Ratios of 1, 2, 4, 5,8, 10, 16, 20, 32, 40, and 80Meets ANSI TIA/EIA-644-A-2001 LVDS Standard RequirementsPower Consumption: 410 mW TypicalOutput Enable Control for Each OutputSDA/SCL Device Management Interface48-pin VQFN (RGZ) PackageIndustrial Temperature Range: –40°C to +85°C

Description

AI
The CDCL1810A is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT= FIN/P, where P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80. The CDCL1810A supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled. With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810A can support a single-ended clock input as outlined inPin Configuration and Functions. All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only. The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810A is available in a 48-pin QFN (RGZ) package. The CDCL1810A is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT= FIN/P, where P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80. The CDCL1810A supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled. With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810A can support a single-ended clock input as outlined inPin Configuration and Functions. All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only. The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810A is available in a 48-pin QFN (RGZ) package.