Catalog(8 parts)
Part | Number of Circuits▲▼ | Type | Operating Temperature▲▼ | Operating Temperature▲▼ | Package / Case | Divider/Multiplier▲▼ | Divider/Multiplier▲▼ | PLL▲▼ | Frequency - Max▲▼ | Mounting Type | Supplier Device Package | Ratio - Input:Output▲▼ | Ratio - Input:Output▲▼ | Differential - Input:Output▲▼ | Differential - Input:Output▲▼ | Input | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Output | Package / Case▲▼ | Package / Case▲▼ | Package / Case▲▼ |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-SOIC (0.209", 5.30mm Width) | 38000000 Hz | Surface Mount | 16-SO | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | |||||||||
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-DIP | 38000000 Hz | Through Hole | 16-PDIP | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | 0.007619999814778566 m, 0.007619999814778566 m | ||||||||
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-TFSOP | 38000000 Hz | Surface Mount | 16-TVSOP | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | 0.004394200164824724 m, 0.004399999976158142 m | ||||||||
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-TSSOP | 38000000 Hz | Surface Mount | 16-TSSOP | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | 0.004394200164824724 m | 0.004399999976158142 m | |||||||
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-DIP | 38000000 Hz | Through Hole | 16-PDIP | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | 0.007619999814778566 m, 0.007619999814778566 m | ||||||||
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-SOIC | 38000000 Hz | Surface Mount | 16-SOIC | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | 0.003911599982529879 m, 3.900000095367432 ul | ||||||||
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-SOIC (0.209", 5.30mm Width) | 38000000 Hz | Surface Mount | 16-SO | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | |||||||||
1 ul | Phase Lock Loop (PLL) | 125 °C | -40 °C | 16-TSSOP | 38000000 Hz | Surface Mount | 16-TSSOP | 1 ul | 3 ul | CMOS, TTL | 3 V | 5.5 V | CMOS, TTL | 0.004394200164824724 m | 0.004399999976158142 m |
Key Features
• ESD Protection Exceeds JESD 222000-V Human Body Model (A114-A)1000-V Charged-Device Model (C101)Choice of Three Phase ComparatorsExclusive OREdge-Triggered J-K Flip-FlopEdge-Triggered RS Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionOptimized Power-Supply Voltage Range From 3 V to 5.5 VWide Operating Temperature Range From –40°C to +125°CLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human Body Model (A114-A)1000-V Charged-Device Model (C101)Choice of Three Phase ComparatorsExclusive OREdge-Triggered J-K Flip-FlopEdge-Triggered RS Flip-FlopExcellent VCO Frequency LinearityVCO-Inhibit Control for ON/OFF Keying and for Low Standby Power ConsumptionOptimized Power-Supply Voltage Range From 3 V to 5.5 VWide Operating Temperature Range From –40°C to +125°CLatch-Up Performance Exceeds 250 mA Per JESD 17
Description
AI
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.