74AHC16373 Series
16-Bit Transparent D-Type Latches With 3-State Outputs
Manufacturer: Texas Instruments
Catalog(3 parts)
| Part | Operating Temperature▲▼ | Operating Temperature▲▼ | Mounting Type | Supplier Device Package | Delay Time - Propagation▲▼ | Package / Case | Logic Type | Circuit | Output Type | Current - Output High, Low▲▼ | Current - Output High, Low▲▼ | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Independent Circuits▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
-40 °C | 85 °C | Surface Mount | 48-SSOP | 9.999999717180683e-10 s | 48-BSSOP (0.295", 7.50mm Width) | D-Type Transparent Latch | 8:8 | Tri-State | 0.00800000037997961 A | 0.00800000037997961 A | 2 V | 5.5 V | 2 ul | |
-40 °C | 85 °C | Surface Mount | 9.999999717180683e-10 s | 48-TFSOP | D-Type Transparent Latch | 8:8 | Tri-State | 0.00800000037997961 A | 0.00800000037997961 A | 2 V | 5.5 V | 2 ul | ||
-40 °C | 85 °C | Surface Mount | 48-SSOP | 9.999999717180683e-10 s | 48-BSSOP (0.295", 7.50mm Width) | D-Type Transparent Latch | 8:8 | Tri-State | 0.00800000037997961 A | 0.00800000037997961 A | 2 V | 5.5 V | 2 ul |
Key Features
• Members of the Texas InstrumentsWidebusTMFamilyEPICTM(Enhanced-Performance Implanted CMOS) ProcessOperating Range 2-V to 5.5-V VCCDistributed VCCand GND Pins Minimize High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsEPIC and Widebus are trademarks of Texas Instruments Incorporated.Members of the Texas InstrumentsWidebusTMFamilyEPICTM(Enhanced-Performance Implanted CMOS) ProcessOperating Range 2-V to 5.5-V VCCDistributed VCCand GND Pins Minimize High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsEPIC and Widebus are trademarks of Texas Instruments Incorporated.
Description
AI
The 'AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AHC16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AHC16373 is characterized for operation from -40°C to 85°C.
The 'AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AHC16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AHC16373 is characterized for operation from -40°C to 85°C.