74ABT162601 Series
18-bit universal bus transceivers with 3-state outputs
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Number of Circuits | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Mounting Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Supplier Device Package | Operating Temperature▲▼ | Operating Temperature▲▼ | Current - Output High, Low▲▼ | Package / Case▲▼ | Package / Case▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
18-Bit | 0.007493000011891127 m | 0.007499999832361937 m | 56-BSSOP | Surface Mount | 5.5 V | 4.5 V | 56-SSOP | -40 °C | 85 °C | 0.012000000104308128 A, 0.012000000104308128 A, 0.03200000151991844 A, 0.06400000303983688 A | |||
18-Bit | 56-TFSOP | Surface Mount | 5.5 V | 4.5 V | 56-TSSOP | -40 °C | 85 °C | 0.012000000104308128 A, 0.012000000104308128 A, 0.03200000151991844 A, 0.06400000303983688 A | 0.006099999882280827 m | 0.006095999851822853 m |
Key Features
• Members of the Texas InstrumentsWidebusTMFamilyB-Port Outputs Have Equivalent 25-Series Resistors, So No External Resistors Are RequiredState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationUBTTM(Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled ModeLatch-Up Performance Exceeds 500 mA Per JESD 17Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownFlow-Through Architecture Optimizes PCB LayoutPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.Members of the Texas InstrumentsWidebusTMFamilyB-Port Outputs Have Equivalent 25-Series Resistors, So No External Resistors Are RequiredState-of-the-ArtEPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationUBTTM(Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled ModeLatch-Up Performance Exceeds 500 mA Per JESD 17Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 5 V, TA= 25°CHigh-Impedance State During Power Up and Power DownFlow-Through Architecture Optimizes PCB LayoutPackage Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.
Description
AI
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB\ is active-low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT162601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT162601 is characterized for operation from -40°C to 85°C.
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB\ is active-low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot.
When VCCis between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT162601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT162601 is characterized for operation from -40°C to 85°C.