54ACT109 Series
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset
Manufacturer: Texas Instruments
Catalog(1 parts)
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Key Features
• Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
Description
AI
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.