74LVTH273 Series

3.3-V ABT Octal D-Type Flip-Flops With Clear

Catalog

3.3-V ABT Octal D-Type Flip-Flops With Clear

Part	Operating Temperature (Max)	Operating Temperature (Min)	Input Capacitance	Type	Package Name	Mounting Type	Number of Elements	Package Length	Package Width	Current - Quiescent (Iq)	Trigger Type	Number of Bits per Element	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Output Type	Clock Frequency	Current - Output High	Current - Output Low	Max Propagation Delay	Max CL	Function
Texas Instruments SN74LVTH273DWRE4	85 °C	-40 °C	4 pF	D-Type	20-SOIC	Surface Mount	1	0.295 in	7.5 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273DWRG4	85 °C	-40 °C	4 pF	D-Type	20-SOIC	Surface Mount	1	0.295 in	7.5 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273MNSREP	125 °C	-55 °C	4 pF	D-Type	20-SO 20-SOIC	Surface Mount	1	0.209 in	5.3 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273DBR	85 °C	-40 °C	4 pF	D-Type	20-SSOP	Surface Mount	1	0.209 in	5.3 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273PW	85 °C	-40 °C	4 pF	D-Type	20-TSSOP	Surface Mount	1	0.173 in	4.4 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273PWR	85 °C	-40 °C	4 pF	D-Type	20-TSSOP	Surface Mount	1	0.173 in	4.4 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273DW	85 °C	-40 °C	4 pF	D-Type	20-SOIC	Surface Mount	1	0.295 in	7.5 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273IPWREP	85 °C	-40 °C	4 pF	D-Type	20-TSSOP	Surface Mount	1	0.173 in	4.4 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset
Texas Instruments SN74LVTH273NSR	85 °C	-40 °C	4 pF	D-Type	20-SO 20-SOIC	Surface Mount	1	0.209 in	5.3 mm	190 µA	Positive Edge	8 bits	3.6 V	2.7 V	Non-Inverted	150 MHz	32 mA	64 mA	4.9 ns	50 pF	Master Reset

Catalog

3.3-V ABT Octal D-Type Flip-Flops With Clear

Description

This octal D-type flip-flop is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct-clear (CLR)\ input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This octal D-type flip-flop is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct-clear (CLR)\ input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.